Deterministic ICE App Tackles ICE Limitations

A new approach to in-circuit emulation.


Historically, SoC verification has used In-Circuit Emulation (ICE) to exercise the design under test (DUT) by connecting physical targets to an emulator. ICE delivers the advantage of being able to run real-world usage scenarios before tape-out.

However, an ICE-based verification environment is hampered by several inherent limitations. It is restricted to trigger- and waveform-based debug. Waveform visibility is limited to the hardware trace memory buffer supported by the emulator — typically one to two million cycles. An ICE environment is prone to randomness, making it nearly impossible to consistently capture debug information and validate that a bug is fixed. And an ICE environment is relegated to the lab, requiring users to be where the lab is located.

Still, an ICE-based environment is required in many SoC verification scenarios. To address the limitations with ICE in an ICE-based environment, Mentor developed the Veloce Deterministic ICE App.

The Veloce Deterministic ICE App delivers a repeatable and virtual debug flow for an ICE-based environment. It also addresses debug limitations, including randomness, by creating a virtual debug model of an ICE run. It generates a replay database to repeat a test without cabling to the physical ICE targets.


Figure 1: The Veloce Deterministic ICE App use model.

Best of all, the Veloce Deterministic ICE App use model is very simple. It only requires a recompile of the design using Veloce compile switches. There are no changes required to the design RTL or other user code. You can see displays or monitors by enabling them before design compilation.

To generate a replay database, you specify your requirements and enable the Veloce Deterministic ICE App replay mode. Veloce generates the replay database while it runs the standard ICE test case with the ICE targets connected. Once the run is complete, the test case can be run as often as necessary using the replay database without the use of ICE targets.


Figure 2: Veloce Deterministic ICE use model.

To find out more about the Veloce Deterministic ICE App, download the new whitepaper Using the Veloce Deterministic ICE App for Advanced SoC Debug.

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