DFM: Out of the Spotlight and Into the Trenches

By Joe Davis and David Abercrombie

The year is 2006. Everywhere you look, the phrase “Design for Manufacturing” or its acronym, DFM, is being brandished as if it were the banner of some brave new army of chip designers. “DFM is the solution to discontinuity issues at 65 nm.” “Traditional boundaries between design and manufacturing will vanish.” Articles and papers discussing DFM topics reached an all-time high…then started to tail off dramatically (Figure 1). What happened?

Like many other inventions and technologies before it, DFM brought neither salvation nor ruination: it merely transformed the way chips were designed and manufactured. It solved some problems, and exposed others that had previously been hidden from view. So where is DFM now, and what is it doing? Good question…

DFM appears to have laid the trumpet down, had a quick cup of coffee, and gone to work. While the initial kerfuffle often tried to cast DFM as some new, exotic technology, the truth is that a lot of what it contained simply expanded our ability to find potential errors and flaws in our designs, and to improve them before they were cast into silicon. Much of DFM has simply been absorbed into the design and verification flows via expanded design rule checking (DRC) rule decks. Don’t believe us? Just take a look at the evidence (Figure 2).

With the advent of advanced checking technologies such as equation-based DRC and pattern matching, designers can now quickly find issues in designs during verification that used to require lengthy and expensive simulation.

DFM is being used heavily in cell design. If you could somehow calculate yield density on libraries from 130 to 40 nm for a given IP supplier, I’m willing to bet you would see that the yields actually went up because they started performing the equivalent of critical area analysis, critical feature analysis, contact doubling, etc. in the cell design. It’s not really a secret that all the major design houses now perform – DFM on their cells, starting with either 90 or 65nm, often in partnership with the fabs. The reason you don’t hear much about these days is because it is mostly done by a) the foundries themselves, or b) companies under contract to the foundries. But it’s very real.

What about some of those other “sexy” DFM technologies we heard so much about?

• Via doubling. Okay, not so sexy, but everyone does it, so no one bothers to talk about it. Also, if you don’t do it in your design flow, the foundry may do it for you.
• Metal Fill. Most people don’t even think of metal fill as DFM, but it is. In fact, it’s the workhorse of manufacturability in the design world. The “Design” in DFM really comes in when you start finessing the algorithms with respect to critical nets, or when you extract the parasitic impact of the added fill and then recheck timing.
• Lithography and other systematic issues. Most of these checks have made their way into DRC. If you went back and reviewed all the production DRC decks for the 40 nm process at a foundry, you would find that the current deck has hundreds more checks than the original deck. Designers do litho-friendly design (LFD) checks at the end of verification to make sure they didn’t miss anything, but it’s all still within DRC, so you simply don’t hear about it.
• Layout-dependent effects on devices. This problem is real, and getting worse. You do your schematic design, you do layout, you go through LVS to get the device deltas, then you re-simulate and iterate. We’re not talking statistical design here—this is baseline. Then you have variation on top of that. The new problem is that the variation depends on the layout, causing another outer iteration loop on the whole flow.

DFM hasn’t gone away or been discredited, and it isn’t still some unproven set of technologies. It’s just slipped into our bag of tools and become a part of our everyday work flows. And that’s the way good tools should work.

About the Authors

Joe Davis has worked on both sides of the EDA industry—designing ICs and developing tools for IC designers and manufacturers. He is currently the Product Manager for Calibre interactive and integration products at Mentor Graphics. Joe earned his BSEE, MSEE and Ph.D. in Electrical and Computer Engineering from North Carolina State University. When he is not applying his expertise in data visualization and engineering workflow, Joe enjoys sailing, gardening, hiking, and living and working in new places and cultures.

David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics. For the last few years, he has been driving development of EDA tools that can solve the issues in design to process interactions (DFM) that create ever-increasing yield problems. David received his BSEE from Clemson University, and his MSEE from North Carolina State University. He loves to play the guitar, explore the great outdoors, and watch a great science fiction show, but not all at the same time.