Digitizing Memory Design And Verification To Accelerate Development Turnaround Time

By Anand Thiruvengadam, Farzin Rasteh, Preeti Jain, and Jim Schultz

Some digital design and verification engineers imagine that their colleagues working on analog/mixed-signal (AMS) chips are jealous. After all, the digital development flow has enjoyed the benefits of increased automation and higher levels of abstraction for many years. Hand-instantiated devices and manual interconnection were supplanted by logic synthesis and fully automated place-and-route. SPICE runs and gate-level simulations have been almost entirely replaced by sophisticated object-oriented testbenches that generate verification tests automatically. While AMS design tools have advanced as well, the progress has been much slower. Digital engineers can be forgiven for assuming that their AMS counterparts want a more automated solution.

In the case of memory design and verification, there is a lot of truth in this assumption. Recent innovations have resulted in the “digitization” of key parts of the memory development flow. As a recent blog post noted, the demand for more memory and more application-specific variants of memory chips is putting tremendous pressure on development teams. The only solution is to “shift left” the development process, including the adoption of design and verification techniques well proven in the digital domain. While the core memory array continues to be developed using traditional techniques, much of the circuitry on the boundary of the array, beyond the sense amps, is closer to custom digital design than AMS. Applying digital techniques to the memory of the periphery is both logical and practical.

An effective solution for memory development digitization must have several elements. The digital design environment and the AMS design suite must be closely linked, enabling seamless design/place/route of the digital blocks in the memory periphery from within the custom design environment. Once the design is complete, timing-aware place-and-route of the periphery logic both automates a traditionally manual process and replaces tedious analysis loops with an integrated flow. By taking static timing into account during placement and routing, convergence to the desired power, area, and performance (PPA) goals for the memory is must faster and more predictable. Human layout experts can spend their time focusing on the core array and not on the periphery.

On the verification front, a digital-on-top flow enables efficient verification of memory datapaths using co-simulation and digital testbenches. By using a digital abstraction of memory datapaths and selectively switching to analog views for critical blocks and time periods during simulation, datapath verification turnaround time can be greatly improved. There are numerous other benefits of this hybrid flow, including the use of AMS-level noise and signal integrity analysis coupled with static timing. The result is signoff quality characterization, validation, and verification of the complete memory chip, both core array and peripheral logic.

Synopsys provide a complete, robust solution for the design and verification of memories, including digitization of key stages in the flow. Co-design of the digital and AMS portions is provided by Synopsys Custom Design Family and Synopsys Digital Design Family. Designers can take advantage of digital implementation techniques where possible, while not sacrificing the hand-optimized layouts for memory cells and sense amps.

Using Synopsys Custom Compiler, place and route engineers can define the floorplan for the memory chip and then manually place critical cells or nets. The rest of the periphery logic can be automatically placed and routed using Synopsys Fusion Compiler or Synopsys IC Compiler II. This reduces the place-and-route time from days to hours without reducing the QoR. In addition, clock tree synthesis automates the traditionally tedious process of clock hookup. When engineering change orders (ECOs) must be applied to the design, this step takes minutes rather than hours. In addition, Synopsys is working closely with major memory vendors to ensure that the timing-aware place-and-route process takes reliability and aging effects into account.

For verification, Synopsys PrimeSim Continuum provides a unified workflow of next-generation simulation technologies, from gold-standard SPICE to FastSPICE. PrimeSim-VCS co-simulation combines analog and digital simulators to offer high performance mixed-signal simulation. It also offers the capability to swap digital and analog views back and forth dynamically within one co-simulation. That allows running the simulation really fast by using digital views for blocks and swapping some of those views with SPICE only during the simulation periods when SPICE accuracy is needed. This capability, called Real Time View Swapping (RTVS), provides the optimum flexibility to the verification engineer to strike a balance between accuracy and runtime speed during memory datapath simulation.

Memory development teams are being asked to design more complex chip variants all the time, and they can only meet the demanding schedules by shifting as much of design and verification effort as possible earlier in the project timeline. These teams can leverage the long experience of digital chips in automating key portions of the development flow and apply the same techniques to portions of the memory outside the core array. Synopsys is the leader in this digitization process, providing the required automation while linking it closely to the AMS design and verification techniques used for the core. New and novel memories can be developed much more efficiently, consuming fewer resources while reducing time to market.

Farzin Rastehis a principal applications engineer at Synopsys.

Preeti Jain is a senior staff product marketing manager at Synopsys.

Jim Schultz is a senior staff product marketing manager at Synopsys.