High-speed I/O is also important for last level cache management.
Source/Authors: Yifan Yuan (UIUC); Mohammad Alian (Kansas); Yipeng Wang, Ren Wang (Intel Labs); Ilia Kurakin (Intel); Charlie Tai (Intel Labs); Nam Sung Kim (UIUC)
Find technical paper here.
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA.)
“Abstract—In modern server CPUs, last-level cache (LLC) is
a critical hardware resource that exerts significant influence on
the performance of the workloads, and how to manage LLC is
a key to the performance isolation and QoS in the cloud with
multi-tenancy. In this paper, we argue that in addition to CPU
cores, high-speed I/O is also important for LLC management.
This is because of an Intel architectural innovation – Data
Direct I/O (DDIO) – that directly injects the inbound I/O
traffic to (part of) the LLC instead of the main memory. We
summarize two problems caused by DDIO and show that (1)
the default DDIO configuration may not always achieve optimal
performance, (2) DDIO can decrease the performance of non-I/O
workloads that share LLC with it by as high as 32%.
We then present IAT, the first LLC management mechanism
that treats the I/O as the first-class citizen. IAT monitors and
analyzes the performance of the core/LLC/DDIO using CPU’s
hardware performance counters and adaptively adjusts the number of LLC ways for DDIO or the tenants that demand more LLC
capacity. In addition, IAT dynamically chooses the tenants that
share its LLC resource with DDIO to minimize the performance
interference by both the tenants and the I/O. Our experiments
with multiple microbenchmarks and real-world applications
demonstrate that with minimal overhead, IAT can effectively and
stably reduce the performance degradation caused by DDIO.”
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Tools become more specific for Si/SiGe stacks, 3D NAND, and bonded wafer pairs.
Key pivot and innovation points in semiconductor manufacturing.
Thinner photoresist layers, line roughness, and stochastic defects add new problems for the angstrom generation of chips.
The verification of a processor is a lot more complex than a comparably-sized ASIC, and RISC-V processors take this to another layer of complexity.
Less precision equals lower power, but standards are required to make this work.
Open-source processor cores are beginning to show up in heterogeneous SoCs and packages.
New applications require a deep understanding of the tradeoffs for different types of DRAM.
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design.
How customization, complexity, and geopolitical tensions are upending the global status quo.
127 startups raise $2.6B; data center connectivity, quantum computing, and batteries draw big funding.
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Ensuring that your product contains the best RISC-V processor core is not an easy decision, and current tools are not up to the task.
Leave a Reply