Dropping The Voltage: Now What?

It all makes sense from a high level, but sometimes theory and reality aren’t completely in sync; put out one fire, create another.

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By Ed Sperling

Ratcheting down the voltage in an SoC design seems like the simplest way to reduce power consumption, but it doesn’t always work out that way. In fact, reducing voltage can have some rather strange and unexpected effects at all levels of chip design, including testing and debugging.

The problem is that not all parts of the chip work the same way without a minimum amount of voltage flowing through it. Gates don’t shut, current leaks in strange places and power budgets fall apart.

Jan Rabaey, who heads the University of California’s Berkeley Wireless Research Center, said one of the biggest surprises is that reducing voltage can actually increase current leakage.

“Everyone will have to reduce the voltage,” he said. “There is no other way. But one of the major challenges is that for a device to work, the gate must work. If you decrease the threshold voltage, you get more leakage.”

So far, this is relatively new ground for most chip engineers because the main focus has been on performance, not reducing the power of the chip. But he said that will change at future nodes as power budgets become the key competitive differentiator for devices rather than performance.

“There are other challenges, too,” he said. “If you decrease the supply voltage, it is more susceptible to noise.”

The research under way at universities is being mirrored in the corporate world, as well. Rob Aitken, R&D Fellow at ARM, said his company has been working on dropping the operating voltage, but with each step a new problem crops up that has to be solved.

“Similar to what was proposed for synthesis 20 years ago, a lot of these low-power techniques operate by taking slack in the design and stealing it to save power,” said Aitken. “So you lower the voltage, which causes it to run a little slower. That causes paths that were near critical before to become critical. Then you start adding multi-threshold devices to improve the leakage, and the paths start wandering up toward critical again. When you subsequently put things in different power domains, you have a low-voltage domain and a high-voltage domain, and that makes a significant step toward critical.”

Adding multiple power domains only makes the problem worse sometimes.

“When you start doing multiple power domains you can also get weird leakage paths and weird analog behavior where things you think are shut off really aren’t,” he said. “You get strange leakage currents that flow back and forth. When you try to debug this stuff, it helps a lot if you have scan wrappers. Power gating is the other thing that matters a lot in debugging. It’s easy to find out if a switch is turned on. You need to manage the inrush current. So when you have a domain that’s off, if you just flip the switch and it all goes on, there’s a good chance that any state retention you were thinking of has been corrupted by the power bouncing around on the network.”

Still, most researchers are optimistic that these problems can be solved, and often with huge power savings. But exactly what devices will look like in the future, and how many workarounds are necessary to make them work, remains to be seen.

For additional information on this subject, check out Bhanu Kapoor’s blog on verifying low-voltage designs.


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