A Necessary Duo: IP And Assertions

Chips aren’t always used the same way and with the same power-optimization techniques.


By Ann Steffora Mutschler
Assertions are key to complete and accurate verification, as I dove into here, and there are implications for IP as well.

In the case of an embedded processor core that is shipped out as an RTL by the IP vendor, and then used by an engineering team to create a cell phone SoC or to create a consumer SoC for a set-top box or what have you, that core goes into an end application SoC. But that embedded processor core is going to have a different power architecture and control when it is used in one SoC versus another, explained Krishna Balachandran, director of low power verification marketing for Synopsys. “If I am the IP provider, how do I know that when my IP gets implemented by customer ‘A’ versus customer ‘B,’ and they use different power architectures to control that at the chip level, that it will all work properly?”

Connected to this is the lack of control the IP vendor has once that core is with the customer. “How do I know that if they are not supposed to do something, but they are doing it at the SoC level, which will mess up the functionality of my processor that I’m delivering to them. How will I know that? I have no control as an IP vendor,” he said. “This leads to the IP vendor asking, ‘What is going to stop the customer from blaming my processor as the source of the problem for their chip?’ This is what IP vendors have to struggle with.”

When a core gets implemented at the chip level in one design it could have just power gating. In another design there might be a need to control the power much more aggressively, and more drastic measures might be used so the core would be used in a different way to include such techniques as standby, dynamic voltage scaling, back biasing, etc.

“One way to communicate the right behavior and the wrong behavior for my IP is to send along assertions along with my IP about power and about how the power behavior should be. If I’m at the receiving end of that then, even if I don’t know how this thing works, how the processor works in the depths of the logic inside—I’m not going to know that and I shouldn’t have to know that—even then, if I do something wrong when I integrate this in terms of power on my chip, these assertions are going to tell me. On the flip side, on the positive assertions side, if it tells me I’m doing something right that is going to give me a level of confidence that I’m actually supplying power to it properly,” Balachandran said.

“That is what this whole ecosystem needs to think about and to work on a solution where you don’t just ship a design. You’ve got to ship the design plus some spec about how the power should be implemented at the top level. Assertions can be a very good mechanism to transfer this information from one company to the other.”

Also, if there is an assertion failure at the chip level, the engineering team integrating the embedded processor core can send the failure message back to the embedded processor core IP company. “Since they created that assertion they’ll know exactly what went wrong. The debug process will be that much quicker,” he concluded.


~Ann Steffora Mutschler

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