Early Power Budgeting for Live Applications

Today, power and energy efficiency are at the forefront of SoC design. Functional activity has a first-order impact on power. Increasing functional integration requires a comprehensive analysis of power consumption across complex modes of operation. Power inefficiency in any one mode can have a significant impact on the competitiveness of a product or time to market. So designers are looking for a solution that gives early visibility into the power profiles of live applications, such as operating system and firmware boot-up, ultra-high definition video frames, etc., to avoid costly surprises late in the product development cycle.

While power analysis is accomplished by a variety of tools across the entire design flow, early visibility into power is best achieved at the RTL stage. RTL power tools typically consume data acquired from a simulation test bench in order to compute power. Standard file formats used to store activity data include SAIF, VCD and FSDB, but the capacity and performance limitations of these formats make them non-viable for power budgeting of live applications. SAIF does not include temporal information, thus compromising on accuracy. VCD is temporal but inefficient because it is a textual format. FSDB is temporal and a binary format, but the generation of this file can slow down emulators and simulators by more than an order of magnitude.

Methodologies have to employ power roll-ups and projections based on shorter-duration simulation activity data for sub-hierarchies but these are prone to inaccuracy. Hence, a high-performance and high-capacity approach is required to gain early power visibility at RTL for live applications.

An emulator-based activity streaming flow for power analysis can enable RTL designers to compute power profiles of live applications by consuming switching data directly from the emulator without converting to FSDB/VCD formats. Emulators run real application-level test benches, execute long verification cycles, and collect relevant temporal design activity. By replacing file-based activity transfer with a streaming interface, both the emulator hardware and power analysis software tools can run faster. The key benefit of this flow is early RTL power visibility for live applications, which is not possible with a conventional file-based activity transfer methodology.

One such solution that enables designers to do power analysis using emulator based activity streaming is PowerArtist Vector Streaming (PAVES), which is an RTL power “socket” that connects with emulators to enable streaming activity transfer. The PAVES socket interfaces directly with Mentor Veloce emulator’s Dynamic Read Waveform (DRW) API to process activity in parallel while Veloce is running. This high-performance integration enables early RTL power budgeting and gate-level power verification of live applications and designers can make early power decisions and do power budgeting for derivative designs.

Fig. 1. PowerArtist streaming activity flow integration with Veloce Emulator

Using the dynamic API flow, current early access customers have seen runtime performance improvements up to 4.5X as compared to the file-based flow without compromising RTL-to-gate power accuracy.

Designers now can meet and verify their power goals by profiling power of live applications using an emulator-based activity streaming flow which eliminates file-based inefficiency, provides capacity and performance benefits and enables users to do a comprehensive power analysis at RTL and gate-level.