Embedded deterministic test points have been created specifically to deal with embedded compression to reduce pattern volume for compressed patterns.
Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This paper describes an exciting new technology, called EDT (Embedded Deterministic Test) Test Points, which has been developed specifically to work with embedded compression to further reduce pattern volume for compressed patterns. Empirical results gathered across numerous customer designs show that EDT Test Points can significantly reduce compressed pattern counts while maintaining or improving test coverage. These compression improvements are achieved even for designs with the most aggressive embedded compression configurations.
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