More Efficient Design

How to achieve power estimation, reduction and verification in low-power design at RTL.

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Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on their long battery lives. In wired applications, power consumption determines heat generation, which in turn drives packaging costs. If not managed properly, this may have significant impact on the end appliance cost.

The landscape complicates if we also factor increasing component density of ICs, which leads to progressively increasing power density. The challenge is to pack in more while still consuming less and less power. Semiconductor industry projections indicate a 4-6x increase in leakage power for designs today and all available techniques must be applied to meet the goal that average and standby power remain flat as complexity increases.

The goal for the designer is simple – to control power consumption to the extent possible. However, this is just a part of the story and there are more fundamental issues like functionality, testability, manufacturability, area and timing and constraints to be handled. Moreover, modern day designs run into multi-million components and have different teams working on different parts with each team having intermediate milestones which finally determine whether the design and then the chip gets shipped on time or not. This complex web of interdependencies makes it all the more expensive for a design to be modified to accommodate power efficiency. The deadlines are always under pressure from the market and the competitors, which leaves less time and room to maneuver for the designer when it comes to creating a power-stingy design. To read more click here.


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