Electromigration Analysis At Advanced Nodes

First of three parts: High chip performance is accompanied by poor reliability, and very reliable chips cannot demonstrate top performance.


Continuous downward scaling is challenging electromigration (EM) signoff using traditional EM checking approaches. The size reduction of metal line cross sections results in higher current densities, which are governed by technology scaling. With the transition to advanced technological nodes, the widely-predicted decrease in EM lifetime is responsible for the pessimistic performance–reliability paradigm: high chip performance is inevitably accompanied by poor reliability, and vice versa—a very reliable chip cannot demonstrate top performance. EM-induced failure rates of individual segments are used as the measure of EM-induced reliability, and the median time-to-failure (MTTF) of the weakest segment is accepted as the measure for the chip life-time. Using these measures results in a very conservative estimate of the top current density limit that can be used to avoid EM failure in a particular technology node.

We’ll examine the requirements for a new methodology for EM assessment in power grid networks that uses grid redundancy and analyzes the effect of residual stress on EM-induced degradation. Such a methodology has significant implications for 3D IC technology, due to the large residual stress found in these designs, and its effect on EM-induced degradation.
The physics behind EM-induced degradation

EM is a physical phenomenon of the migration of metal atoms along a direction of the applied electrical field. Atoms (either lattice atoms or defects/impurities) migrate toward the anode end of the metal wire along the trajectory of conducting electrons. This oriented atomic flow, which is caused mostly by the momentum exchange with the conducting electrons, results in metal density depletion at the cathode, and a corresponding metal accumulation at the anode ends of the metal wire. This depletion and accumulation happen because atoms cannot easily escape the metal volume.

The rate of EM, as defined by the Nernst-Einstein equation, depends on the atomic diffusivity, meaning different materials are characterized by different rates of EM. Typical interconnect metals, such as copper (Cu) and aluminum (Al), are prone to EM, due to their high self-diffusivity. Refractive metals, such as tungsten, tantalum, and titanium, demonstrate strong resistance to EM.

An interconnect segment is a continuously connected, highly conductive metal within one layer of metallization terminated by diffusion barriers. Thin layers of refractive metals form these diffusion barriers for Cu atoms, preventing them from diffusing into inter-layer and inter-metal dielectrics. When metal wire is embedded into a rigid confinement, which is the case with interconnect metallization, the wire volume changes (induced by the atom depletion and accumulation due to migration) create tension at the cathode end and compression at the anode ends of the line. Over time, the lasting unidirectional electrical load increases these stresses, as well as the stress gradient along the metal line. In some cases, usually when a line is long, this stress can reach a critical level, resulting in a void nucleation at the cathode and/or hillock formation at the anode end of line (Figure 1).

Figure 1. Schematics of void and hillock formation in the metal line loaded by electrical current. Electron flow is from left to right.

Different physical mechanisms can be responsible for generating these damages. In the case of voiding, existing cohesive or interfacial micro-cracks near or at the Ta/Cu interfaces can develop into a void by action of the appropriate stresses. Hillock formation, which is a compression-induced extrusion of metal into the surrounding dielectric that can cause a shortage between neighboring metal lines, can be initiated by micro-cracks in the adhesion/barrier layers. In addition to voids nucleated at the cathode end of line, where a divergence in atomic flux happens (atom flux is terminated at the barrier interface), many voids are nucleated down to the polycrystalline metal line toward the anode end at any location characterized by the atom flux divergence. These are the triple points formed by intersections between grain boundaries (GB) and the top dielectric barrier (typically composed of SiCN), or contacts between three neighbor grains (Figure 2). It is well known that atoms diffuse much faster along GB and interfaces than through the grain interiors, making GBs and interfaces the major venues for EM.

Figure 2. (a): TEM picture of voids nucleated at the top interface (electron flow from left to right), courtesy of E. Zschech of Fraunhofer IZFP-D; (b) and (c): simulated kinetics of the void nucleation at the triple point and growth (electron flow from right to left)

Those triple points where the number of outward diffusion channels exceeds the number of inward channels (point A in Figure 2) can develop a depletion in metal density, leading to possible void nucleation.

Nucleated voids, depending on the local texture of neighboring grains, can grow in size or disappear. As shown in Figure 3, two major mechanisms of void growth are:

  • Scavenging the vacancies that migrate to the void due to the stress gradient between the void surfaces (zero stress) and the surrounding metal (tensile stress),
  • Agglomeration of voids travelling along the metal line toward the cathode end (against the electron flow) due to the capillarity effect.

Figure 3. Simulated growth of the line corner void by scavenging the vacancy flux and agglomerating with the small voids drifting along the top interface.

GBs with different crystallographic orientations are characterized by different atomic diffusivities, governed by a variation in grain crystallography. This variation, together with a random distribution of grain sizes inside metal lines, makes it clear why identical metal lines, characterized by same geometries and same electrical load, demonstrate different time-to-failure (TTF). This TTF represents the instant in time when an increase in line electrical resistance caused by the void growth reaches a critical level (for example, a 10% increase over the original value), as shown in Figure 4.

Figure 4. Effect of voiding on line resistance

To view part two of this series, click here.
To view part three of this series, click here.