Eliminating Software Development Bottlenecks For SoCs

System on chip (SoC) devices, by definition, use a combination of hardware and embedded software to provide their specified functionality. Both the design and programming teams face many challenges and have huge tasks. No matter how well they may perform, the full system cannot be verified and validated until the hardware and software are brought together in the bring-up lab. This is usually way too late in the project for hardware bugs to be found since chip turns cost a fortune and delay time to market (TTM). Finding some software bugs at this stage is inevitable, but it also is too late to start software testing. In addition, dozens or hundreds of embedded programmers all trying to debug their code on a handful of lab bench setups is a major project bottleneck.

To meet today’s competitive TTM requirements, as much software development as possible must be completed before the hardware is available. The bring-up lab should be the place for final validation only, finding and fixing a small number of software bugs related to interaction with the hardware. Emulation and FPGA prototyping are two possible solutions, and they play critical roles in many SoC projects. Embedded software can be tested and debugged efficiently on these platforms well before the SoC has been taped out. However, there is still an access bottleneck since most projects can’t afford to replicate the platforms across the programming team. In addition, the register transfer level (RTL) design must be close to completion to be mapped into these platforms, so this cannot take place early in the project.

It may be possible to test and debug the software on processor models running in RTL simulators, which are easier to replicate. However, this runs very slowly, creating performance bottlenecks, and also requires a fairly complete design. What SoC projects really need is a simulation-based approach that doesn’t require the RTL design. This allows hardware and software development to start and proceed in parallel, coming together for co-verification and pre-silicon validation in emulation or FPGA prototyping. If the software effort is the dominant factor in the schedule, it can even begin before RTL coding starts, following the architectural phase of the project.

Virtual prototypes have emerged as the best solution for eliminating all these bottlenecks. A virtual prototype is an abstract software simulation model of the SoC hardware, containing fast instruction set simulators (ISSs) for the embedded processors. Virtual prototypes need to model all architecturally visible registers and any other hardware features with which the embedded software directly interacts. They do not need to include the many implementation details required in RTL models used to create actual chips, so they can be developed earlier and more easily. Because virtual prototypes model the complete hardware software interface (HSI), they can run the same production software that will run in emulation, FPGA prototypes, the bring-up lab and the field.

Because of their abstract nature, virtual prototypes are fast, with execution speed rivalling that of hardware platforms. Users can boot operating systems and run applications (apps) on top of the low-level software that accesses the HSI. Complete software stacks can be tested and debugged. For even better performance, device virtualization can replace register accurate models when the HSI is not being tested. Virtual prototypes run on standard hosts, typically personal computers (PCs), so cost of deployment is low and there is no specialized hardware to build or maintain. They can be replicated quickly and inexpensively across distributed programming teams, parallelizing development and fostering collaboration.

Synopsys Virtualizer satisfies all the requirements for creating and debugging a state of the art virtual prototyping solution. Its fast simulation speed enables testing and debugging embedded software all the way up to the apps level. It supports device virtualization using VirtIO, the standardized open interface for simplified input/output devices. By replacing the detailed device drivers with the VirtIO models, higher level software runs even faster in the virtual prototype. The industry’s richest set of standard models for several types of devices, including disk drives, human input devices such as keyboards and mice, and graphics processing units (GPUs) are included as part of Virtualizer.

Broad support of virtual prototype models for many widely used processors enables the highest productivity through fast, register accurate simulation, advanced debug and analysis, and synchronized integration with third party software debuggers and embedded software development tools. Creation of custom virtual prototypes is handled through an easy-to-use IDE by enabling efficient modeling for blocks, rapid assembly into a virtual prototype of the system, and automated packaging of the model for easy distribution.

Several unique features further enhance efficiency and usability, including:

• Extensive scripting support, supporting tasks such as error and fault injection
• Hybrid emulation and prototyping with Synopsys prototyping and emulation solutions
• Checkpoint and restore of platform state, very useful for skipping long initialization phases and jumping directly to times of interest for debug purposes
• A built-in debugger specialized for use with virtual prototypes
• Connection to real-world devices and interfaces such as PCI Express and Ethernet
• Fast Track, which quickly detects bugs in configuration or usage

Finally, support for continuous integration (CI) enables merging all working copies of the software into a shared codebase several times a day. Python application programming interfaces (APIs) are available for all features to help develop CI scripts for software build and test systems. CI reduces the effort needed to merge and synchronize updates from multiple programmers, further increasing efficiency and reducing TTM. Virtual prototypes have proven to be the best way to eliminate the traditional bottlenecks associated with software development. For more information and deeper detail, a recent white paper is available.