tag: instruction set simulator

Eliminating Software Development Bottlenecks For SoCs
By Sam Tennent - 23 Nov, 2021 - Comments: 0

System on chip (SoC) devices, by definition, use a combination of hardware and embedded software to provide their specified functionality. Both the design and programming teams face many challenges and have huge tasks. No matter how well they may perform, the full system cannot be verified and validated until the hardware and software are brought together in the bring-up lab. This is usually wa... » read more

RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV
By Lee Moore - 29 Jul, 2021 - Comments: 1

By Lee Moore and Simon Davidmann The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end application needs and requirements. RISC-V has a modular structure with many standard instruction extensions for additional dedicated hardware features such as Floating... » read more

New Uses For Assertions
By Ann Mutschler - 24 Sep, 2020 - Comments: 0

Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification engineers have used assertions in specific ways. First, there are assertions for formal verification, which are used by designers to show when something is wrong. Those assertions help to pinpoint wh... » read more

Practical Processor Verification
By Brian Bailey - 23 Apr, 2020 - Comments: 0

Custom processors are making a resurgence, spurred on by the early success of the RISC-V ISA and the ecosystem that is rapidly building around it. But this shift is amid questions about whether processor verification has become a lost art. Years ago custom processors were common. But as the market consolidated around a handful of companies, so did the tools and expertise needed to develop th... » read more

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