Embedded World 2023: It’s Time To Architect All Ambitions With Custom Compute

As soon as we arrived in Nuremberg, we could feel the city was buzzing and ready for a great Embedded World 2023 conference. It was hard to avoid exhibitors, speakers, and visitors at breakfast in the hotel or at dinner in restaurants – not to mention the waves in the metro! It was my first time at the conference, and I found the number of attendees and the quality of discussions very satisfying – an impression that was confirmed by everyone I had a chance to talk to.

Is the momentum for RISC-V continuously growing? Yes. Is the idea of design freedom getting more and more attention? Yes. Is customization the only way forward? That’s what we believe in at Codasip, and it was great to see how well this message resonated within our audience at the conference.

Architecting all ambitions with custom compute

‘Architect your ambition’ is a tagline you should get used to. As our Chief Commercial Officer Brett Cline explained in his talk at the exhibition forum, differentiation is the key to success and customizing the hardware to a specific workload is the only way to innovation. Custom compute is not new – there are leading references in the mobile or automotive industry today. What is new however, is the approach. As Brett explained, it is the combination of the open RISC-V ISA, processor design automation, and high-quality processor IP that makes the difference.

Brett Cline presenting at the Embedded World 2023 exhibition forum.

The open era of (custom) computing

The potential of custom compute is indisputable. But before we dive deeper into the customization topic, let’s pause for a second and look at RISC-V.

The team at the Codasip stand.

At Embedded World 2022, we thought the RISC-V genie was out of the bottle. With DAC 2022, RISC-V was everywhere, and we asked whether it was too risky not to adopt RISC-V. At the end of 2022, the RISC-V summit also showed that RISC-V is inevitable. A few months later, all of this is still true, and even more. In her talk at the RISC-V pavilion, Calista Redmond, CEO of RISC-V International, said, “RISC-V is inevitable. This is the open era of computing.” Almost all visitors at our stand knew about RISC-V and understood its modularity and potential in terms of design freedom. We just had to focus on the ‘how.’

Another observation from conversations with media and customers was about the RISC-V ecosystem. We heard several people express awe at the way this ecosystem has developed and at the speed it happened. Thanks to the members of the ecosystem collaborating to add their unique expertise, complete and implementable RISC-V solutions are no longer a roadmap bullet, they are available here and now.

A safe and secure custom compute approach

Walking around the different exhibition halls, it was obvious how big and how essential security and safety as well as optimization are in the embedded space.

We had two demos at our stand. One shows an example of dual core lock step (DCLS) implementation using a customizable RISC-V core, demonstrating fault trapping and detection for safe and secure applications. We built this reference design using ISO 26262-certified tools from IAR. Our other demo showed an example of CPU customization for FIR filter acceleration, demonstrating PPA improvements achieved with design automation.

Both demos are based on Codasip L31, a low-power, general-purpose, embedded RISC-V CPU providing an ideal balance between performance and power consumption. This core is customizable with Codasip Studio for use in IoT devices, industrial and automotive control, or as a deeply embedded core in a larger system.

Growing interest in RISC-V customization, the only way forward

We’ve been focusing on the exhibition so far, but let’s not forget a major part of this event: the Embedded World technical conference. This year we were very proud to have three accepted papers. It was a great opportunity for us to discuss RISC-V customization with a highly interested audience. Our CTO Zdenek Prikryl presented three different topics that all caught the attention of the session participants. The number and quality of the questions raised on customization really confirmed that ambitious innovators will have to adopt custom compute to shape their successful products.

Technical talks by Codasip at the Embedded World conference.

• Talk 1: Adding RISC-V custom instructions post-silicon through eFPGA (joint talk with Menta). Read the technical paper on customization with eFPGA.
• Talk 2: A multi-layered methodology to address challenges linked to RISC-V most attractive feature (joint talk with Siemens). Read the technical paper on RISC-V verification.
• Talk 3: Creating a domain specific core with RISC-V custom instructions for powerful local AI. Read the Mythic case study.

All in all, it was a great week at Embedded World 2023. It was great to see so many visitors interested in all the innovations across the industry presented at the conference, especially around RISC-V. RISC-V is here and well understood – no doubt – and our team at Codasip is proud of our unique custom compute approach. We look forward to meeting you next at the European RISC-V Summit in Barcelona, in June 2023.