Enabling A Chiplet Supply Chain

Chiplets have been in the news quite a bit lately. A chiplet-based architecture offers several advantages that chip designers can benefit from as they bring out new products to the market. Over the years, system designers have integrated more and more functions into a system on chip (SoC). As a result, the size of SoCs keeps increasing. Even though SoCs provide several advantages in performance, they come with a very big drawback. The drawback is that as the die size keeps increasing, the yield of the chip takes a significant hit. Some of the latest SoCs today are almost reaching the reticle size. Such a large die size typically results in very poor yield for the product. Chiplets provide the solution with smaller die sizes.

The need for a chiplet architecture

Some of the other advantages of using a chiplet architecture is that it can provide the same benefits of a system on a chip but without spinning out a whole new chip. Each tape-out for the latest process node can cost millions of dollars. Package-level integration today can become the new SoC with different dies and a scalable solution. Furthermore, a chiplet-based design’s performance can be much better than individual discrete chips on a board. It may be comparable to an SoC in performance, where it offers lower power, lower bit error rates and higher bandwidth when compared to a discrete solution on a board. See figure 1.

Fig. 1: An open chiplet platform on a package. Source: UCIe Consortium.

A chiplet also reduces time to market for a solution. System designers can use different dies from different process nodes and different technologies in a chiplet architecture. This flexibility is not available in an SoC. A chiplet-based architecture also allows use of the most appropriate technology for a given solution without the complications of putting together different technologies on the same die. Using different dies from different suppliers can also reduce development cost since it allows the use of readily available, off the shelf designs rather than the integration of a new product. Typically, it also results in a better yield compared to a larger SoC. Many times, such a solution is also customizable. So, for different requirements, customers can use or tweak the solution for the best performance. There are different types of solutions available in the market for a chiplet architecture. For example, a chiplet can be substrate based (figure 2a), silicon bridge based (figure 2b), interposer based (figure 2c) or a redistribution layer (RDL) based design (figure 2d).

Fig. 2: Different chiplet design approaches. Source: UCIe Consortium.

Challenges associated with chiplets

A chiplet architecture is not necessarily a panacea for chip designers. It comes with its own set of challenges. Any time one design team configures a heterogeneous solution with several different sources of silicon and someone else does the assembly, it is a challenge to assign ownership of the whole solution. Any such solution also needs to be simulated, which includes different process nodes – perhaps different silicon technologies and assembly processes all altogether. When integrated device manufacturers (IDMs) design their own multi-chip modules (MCMs), they have control over the location of the I/Os and the way routing is done between the two chips. In case of chiplets, the interface and I/Os between different suppliers may not be optimized for power or noise. Standardization of interfaces will be instrumental in adoption of these building blocks and the success of this approach to build new products.

More and more suppliers are getting concerned about security aspects of their products. With an IDM, installing security measures is manageable, since access to testing and assembly sites can be limited. For chiplets, it is much harder to ensure secure procedures, since there are many more players involved in the manufacturing process and more touch points along the way.

Power is another consideration. The latest silicon products coming to market have increased power consumption. Managing the thermal characteristics and understanding the total power dissipation of the solution is important in today’s applications. Some parts of the solution may dissipate more heat. Different chiplets may have different die thicknesses. Finally, the use of different thermal interface materials to extract heat out of the whole solution is important. How the thermal management aspect of a chiplet solution will be handled is still unclear. If the chiplet is designed specifically for a single application or purpose, it loses one of the key advantages of chiplet architecture – it becomes a custom solution similar to what IDMs have been doing already.

What does a chiplet supply chain look like?

When a product has a single die, the solution is very simple. An IDM could do the fab and assembly, or with a design house, it may have the fab, substrate or interposer supplier along with an outsourced semiconductor assembly and test (OSAT) supplier involved in manufacturing and testing of the product. For a multi-chip module, it gets a little more complicated. However, in many cases, it is the same die supplier along with maybe a substrate supplier working with an OSAT to do the assembly.

Chiplets are even more complicated because different die suppliers might be supplying SoCs, memory, I/O or ASICs. Next, there are separate substrate or interposer suppliers, in case it is an RDL based solution. Finally, there may be engagement with an OSAT or fab. With new embedded bridge structures, there may be an extra layer of complexity. In addition, an integrator will source all these different materials and then assemble the solution together. As a result, the complexity of such a solution becomes exponentially high. In the case of multi-die assembly, there are test procedures involved in each step along the way. The die suppliers probe the die and supplying the Known Good Die (KGD) map. Once the assembly starts, every stage after the assembly may require some kind of probe or test to make sure that the assemblies are still functional. At the end of the product assembly, there needs to be a system level test (SLT) to make sure the whole system functions as designed. So, the supply chain gets complicated and a lot more players are involved for chiplet assembly. As the industry develops these solutions and they get more traction in the market, it is important for clear definition of who is supplying what to whom, what are the deliverables and how to resolve issues as they arise. Supply chain considerations have even more importance now with all the geopolitical tensions growing. The trend towards regional supply chains throws another wrench into the whole ecosystem. See figure 3.

Fig. 3: Ecosystem block diagram.

What needs to be done?

Chiplet-based architectures are not new but different suppliers’ capabilities have not been tested. Most of the solutions that have been built so far have been implemented by IDMs, so some of the complexities of assembly that were discussed earlier have not been tested yet either. The UCIe (Universal Chiplet Interconnect Express) Consortium’s UCIe standard is a step in the right direction of putting all the requirements for chiplets in one place, so that different suppliers have a clear idea of what to expect.

In any business decision, the cost of the solution has a major implication on the viability of the product. If such a solution is cost prohibitive, then it will not be successful in the market. Cycle time is another consideration that a lot of chiplet suppliers are getting their hands around. If the assembly of the final product is done at various places instead of under one roof, then the cycle time suffers. It may also result in higher assembly costs. Most of the chiplet-based designs today are for data centers, which are less cost sensitive. For more cost-sensitive applications, such as consumer or automotive applications, more design aspects need to be considered to make the whole assembly cost competitive.

Chiplet solutions exist today in the market. However, these are still custom designs ­– not off the shelf parts that people can obtain from the commodity market to build products. For chiplets to really succeed, interoperability and standardization are must haves. The UCIe Consortium is working towards that goal and the next couple of years will determine the success of these efforts.