Ensuring Signal And Power Integrity In Today’s High-Speed Designs

Leading-edge chip desiLeading-edge chip design was never easy, but it’s getting harder all the time. Rapid advances in communication systems are driving data rates higher. With the emergence of artificial intelligence (AI) applications and the increased need for data processing, high quality data transfer is increasingly critical. Faster data rates and more complex protocols are exacerbating signal integrity and power integrity (SIPI) compliance challenges, necessitating the need for smart design and analysis automation tools. The following figure shows just one example: the growing requirements of compliance to standards over the generations of double data rate (DDR) memories.

In simple terms, SIPI is all about keeping the data and power supply clean, minimizing crosstalk, noise, jitter, and inter symbol interference (ISI). High-performance systems with interconnects between package, substrate, PCB, and backplane, including multi-die systems, require checking for signal and power rail quality or else risk failure. Uncovering SIPI problems in the bring-up lab is far too late in the project; issues must be detected with pre-silicon analysis. Design engineers use signal and power integrity tools to detect system design issues earlier in the simulation phase. This minimizes the risk of a chip turn due to SIPI bugs, shortening time-to-market (TTM).

Engineers must ensure that high speed data is transferred with accuracy and integrity, and this is where SIPI EDA solutions come into the picture. For a chip designer testing an I/O Interface IP, a memory input/output (I/O), or a controller I/O, signal and power integrity are critical. The same is true for a printed circuit board (PCB) engineer checking if the channel on the PCB can do its job of data transfer efficiently with the data intact. Both must ensure signal quality and must address in the simulation phase any potential problems arising from signal degradation due to higher data rates, including:

• Complex crosstalk and ISI due to proximity to adjacent wires
• Reflection and ring back due to impedance mismatch, duty cycle distortion, and jitter induced due to nonlinear buffers
• Imperfect supply causing voltage level bounce resulting in noise and jitter in the system

To accelerate time to signal and power integrity compliance, any effective SIPI solution must meet three critical requirements.

• Offer a complete end-to-end SIPI flow with a silicon-accurate golden simulator that provides comprehensive analysis and extends to 2.5D/3D multi-die systems
• Include in the end-to-end-flow an analysis environment that enables results viewing, probing, and processing of large amounts of SIPI simulation data
• Provide an ability to “shift left” protocol-aware compliance verification and intuitive system debug early during pre-silicon phase

Synopsys PrimeSim HSPICE and its integration with PrimeWave Design Environment meet all these needs. PrimeSim HSPICE for silicon-accurate transistor-level simulation, and a key component of the PrimeSim circuit simulation family, provides several critical capabilities:

• Co-evaluation of signal and power integrity with capabilities to
  • accurately account for ultra-low bit error rate (BER) measurements critical for compliance
  • model non-ideal effects such as noise and jitter
  • calculate power supply induced jitter to be used in timing budgets
  • capture input data independent periodic noise from the power supply
  • inject a wide variety of jitter all of which are enabled through AC, transient, and StatEye multi-domain analyses
• Accurate SIPI transient and statistical analysis with ability to simulate I/O models at different levels of abstraction at behavioral or transistor on the same system design
• Address non-linearity in bias dependent channels such as PAM3/PAM4 and run 1000x faster than transient analysis with StatEye
• Support for memory, serializer/de-serializer (SerDes), MIPI, optical, and multi die systems designed on different technology nodes

Synopsys PrimeSim SPICE is the GPU-accelerated high-capacity engine helpful to simulate large scale systems with post layout parasitics to enable final verification in full transistor level in a practical amount of time. Both simulators can be run in batch jobs on a server farm or the cloud to reduce turnaround time and further shift left the project. Users can easily build scripts to control how many jobs they want to submit at a time. They can also control the number of jobs launched on to each server and check whether they are completed before submitting the next set.

Synopsys PrimeWave Simulation Environment can be used to set up simulation variables and parameters, choose their simulator of choice, and set up analysis in multiple domains such as time, frequency, and statistical to complete a simulation view from all the possible angles. Synopsys WaveView can be used to visualize simulation results and to compare and measure design parameters.

With these capabilities and more, designers can be sure that they are producing a chip that will meet all requirements for standards compliance and work in the bring-up lab on first silicon..

To learn more, join the Signal and Power Integrity Special Interest Group.