Estimating Power And Performing Optimization

Power analysis and optimization have gained importance over the last few years. During this time it has become obvious how critical it is to use realistic payloads to accurately estimate power and perform optimization tasks. Designers have a range of different objectives and concerns when it comes to power. On one side, a team wants to ensure that the average power of their chip is low enough to ensure long battery life. On the other, a team’s main concern may be to prevent local inductive voltage drops that corrupt the functionality of the chip. What is true in all cases is that any analysis performed with insufficiently realistic vectors leads to erroneous conclusions and decisions.

One of the most widespread power analysis tasks consists of estimating the average power of the entire chip over long periods of time. This is typically done to ensure a competitive advantage with a low energy consumption chip that ensures increased battery life, lower energy bills, and/or easier cooling. It can clearly become challenging to generate representative payloads via simulation, and it is not unusual to have designers adopt a divide and conquer approach where they collect data for different sub-blocks that are combined in a spreadsheet. Whether or not this approach can be trusted is a question design teams anxiously ponder until they get their chip back from the fab.

Figure 1: Different types of power estimates

In other cases, peak power is of interest (cf. Figure 1). When it comes to peak power, the necessary analysis can vary widely in spatial and time scopes depending on the nature of the issue. As an example, the problem could be a local and rapid phenomenon, such as a voltage drop (resistive or inductive) that can arise within one clock cycle. Or it could be a more global issue, such as the violation of supply integrity when the current is above a given threshold for more than, let’s say, a few microseconds. The peaks to identify could also be fairly wide apart if the concern is thermal dissipation. Also, if the spatial scope is smaller than the entire SoC, designers will want to identify the local hot spots and thus perform a hierarchical analysis (cf. Figure 2).

Figure 2: Local hot spot identification

Finally, on top of the space and time scope considerations, designers are sometimes interested in measuring not only the power levels, but also the rate of change. This is because the inductive component of voltage drops is becoming as critical as the resistive component at advanced technology nodes (cf. Figure 3).

Figure 3: Voltage drop types

On top of all the power estimation objectives listed above, using representative activity data is also critical for relevant power verification and optimization tasks. For example, it is not uncommon to see dozens of power domains (some using retention) and complex clock schemes in a very complex SoC. In this case, and in particular when the power controller is software-based, the ability to consider actual system usage and interpret power intent in the form of the Unified Power Format (UPF) is key to complete power validation.

For power reduction at the RTL, the same is true. Most, if not all, techniques used to reduce power are very sensitive to the estimated levels of activity at the signal level. Deciding if a stability or an observability condition should be leveraged directly for data gating or clock gating depends on the probability of those conditions. Therefore, designers need to consider realistic system payloads before accepting a modification suggested or implemented automatically by a tool.

Introducing emulation. With an emulator, it is possible to get visibility on all the signals in a design and extract this information for power analysis. In addition, with a high-capacity emulator it is even possible to consider SoCs in their entirety.

The vast array of features offers a viable solution for many of the objectives listed above. It is, for instance, possible to analyze the power of a system emulated with in-circuit emulation (ICE) and virtual emulation. With software debug tools like Veloce, users can even stimulate their IPs from an abstract CPU model running in software.

For example, users can generate and measure the activity of their GPU while running a benchmark on Android. With specialized debug tools, they can correlate the power events observed in the emulator with the lines of code running on a CPU. An emulator also provides the ability to run at full emulation speed and then replay the interesting parts at different speeds to generate more detailed information for power analysis and optimization.

Over time, IC designers have been refining their power methodology and are searching for ways to improve the quality of results. Analyzing vectors corresponding to representative uses of the chip is essential for generating trustable power numbers and meaningful power reduction suggestions. This is why emulation is now a must-have for power analysis.

Read more about using emulation to achieve a more accurate and reliable power methodology in the whitepaper, Using Emulation for Meaningful Power Analysis.