Evaluation Platforms Key To Complex IP Integration

New methodologies and approaches are needed to simplify and speed up the process.

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Just because a chip is complex to build doesn’t mean it has to take a long time.

Runaway complexity in SoC and ASIC design is forcing chip companies to consider different methodologies and approaches that could actually simplify and speed up the whole process.

The first step in this process was commercial IP, and its growing popularity attests to the fact that chipmakers are looking for ways to reduce complexity and leverage what’s already designed and tested in silicon. In fact, it’s not unusual to see as many as 100 separate third-party IP blocks in a complex design these days. Nor is it unusual to find that not all of the pieces work together as planned, or they aren’t characterized sufficiently, or that some pieces work well in some designs and not others.

IP has its quirks. Put it in the context of 100 other IP blocks, shrink them all down to the point where there are physical and proximity effects, noise, electrostatic discharge concerns, electromigration, and those quirks can do everything from impair signal integrity and reduce performance, to even kill a chip.

Since the introduction of Moore’s Law, most chips have been designed to be functionally correct within the bounds of a PPA—power, performance and area—equation. What’s changed, particularly at advanced process geometries and with the increased focus on consumer-driven applications, is that while performance and cost still matter, they don’t matter as much as getting a chip out the door. Miss a market window and you can lose it forever. Miss a market window with a chip that costs $15 million in NRE and you’re likely to cause problems for yourself, your team, and your company.

Even power doesn’t matter as much for many applications, although it will certainly rise in importance as the Internet of Things begins taking root. No one wants to plug in a wearable device every night. But compared with on-time delivery, power takes a back seat. Power can be fixed. Market windows cannot be reclaimed.

So how do we, as an industry, move the ball forward faster? The answer is bigger blocks. These aren’t subsystems, per se. They’re reference designs and platforms, based upon multiple IP blocks that are integrated and proven to work in certain ways. The value for most chipmakers isn’t in choosing standard IP blocks and configurations, such as in the case of SerDes design. The value is in having complete reference evaluation platforms, including boards, test chips, and characterization data, that prove the viability of the IP in advance. These platforms bring all aspects of the technology together, verifying the electrical and functional aspects of the IP so that challenges in designing a complex ASIC/ SoC can be managed with a predictable schedule.
Understanding how basic pieces go together isn’t where chipmakers add value, but it does change the value of what they deliver because it gets everything out the door faster with a proven and well-tested formula. Time is the critical factor, and the semiconductor industry needs to apply some of the incredible innovation it has shown over the past half-century in speeding up time to market. That’s the new bottleneck, and it will require a different way of doing things to solve this problem.