Executive Insight: Adnan Hamid

System-level verification is the new horizon for verification technologies, and Breker has been in this field longer than anyone else.

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Semiconductor Engineering sat down with Adnan Hamid, founder and CEO of Breker Verification Systems. Breker was founded in 2003 and has been concentrating on the creation of verification methodologies for multiprocessor SoCs using graph-based entry methods – something that became a hot topic at DVCon 2014 after Mentor Graphics decided to donate its format to Accellera for standardization.

SE: What keeps you up at night?

Hamid: What is keeping my customers up at night is trying to get products out of the door, getting them right and that means verification. They know they are behind and they need to do something different. What keeps me up at night is finding out ways to get them to switch over to a new paradigm. I need to get them to stop using a few directed tests and instead use program generation for system testing.

SE: Startups often blaze the trail and others reap the benefits of their efforts. How do you make sure this doesn’t happen?

Hamid: This is exactly the topic of the Innovators Dilemma (Clayton Christensen – The Innovator’s Dilemma) and I don’t think there is a magic bullet here. The innovator hopefully knows more about the problem and understands the question better, so they can build better answers.

SE: Are you seeing an uptick in adoption?

Hamid: Definitely. Many companies have recognized they have a big problem. They have seen the impact that randomization had on the design verification group and they want to be there as well. Failures are real. SoCs are often logging over a hundred bugs after the first silicon comes out. Nearly half of them are found by their customers, and this is not what you want to have happen; 30% of problems are found within the DV group, another 20% by the chip company’s software team, which is not their focus and takes a lot longer to debug. What did it take for companies to switch from schematic capture to logic synthesis? At some point the problem just became too big and it was logical to move to a different solution.

SE: Is this driven by productivity or quality?

Hamid: If you look at what the system-level verification guys do, the emulation guys, the design verification guys – they all spend their time trying to come up with test cases and debug them, and the bulk of the time is spent dreaming up the test structure. System-level test cases get complicated. It is no longer about a single UART that you want to make do something, it is more like a camera using a JPEG decoder going to a display. So the primary story is productivity because it takes too long to write tests by hand.

SE: Viable products often have many bugs, but they are good enough. Are you trying to get them from adequate to better?

Hamid: That is missing the point. The industry should pat itself on the back because chips do not have hundreds of thousands of bugs. Hundreds is quite amazing given the amount of logic these systems contain. Yes, there are cases where a company has a chip and they also ship the driver for it, and many issues can be fixed or hidden in that driver. The issue is not do we need to get to perfect quality; the issue is time to market. In many cases, if the software team finds something, it takes too long for them to figure out if it really is a problem and we need to improve that situation.

SE: You recently launched a silicon verification product. How is this a productivity tool?

Hamid: One way to look at it is that you need to find the limitations of your chip. We can’t simulate these things and this is a big problem for the industry. Emulation and FPGA prototyping try to fill this gap. But things fall through and you need to characterize what works in the chip. This saves the software guys from finding the problems, they are already known, so this still helps get the product out of the door faster.

SE: Mentor recently announced it has donated its graph-based format to Accellera for standardization. What are your feelings about this?

Hamid: Breker is fully participating in the Accellera Portable Stimulus Specification Proposed Working Group (PWG). We have two reservations. The first is the narrowness of the proposed standard because it defines stimulus without coverage closure. The second reservation is the possibility that it’s too early for a standard, which might stifle innovation. However, we believe that it’s up the user community to decide what sort of standard they need and when. If Accellera moves toward standardization with the formation of a Working Group (WG), Breker will continue to participate actively, become an Accellera member, and donate our syntax for graph specification.