Existing Circuit Styles Shed Light On Low-Power Design

Adiabatic and asynchronous designs are now getting a serious second look.


By Cheryl Ajluni

Given the growing importance and impact of portable, battery-operated devices in today’s society, it’s easy to understand why power consumption has become such a critical factor in IC design.

But it’s not just battery-operated devices that are driving the need for low-power design. In non-portable devices, the cost of providing power and the increased area resulting from the large heat sinks required to dissipate large amounts of power are further prompting interest in power reduction. Luckily, a number of classical approaches are available to designers looking to reduce power consumption, whether that means utilizing sleep/standby modes, a die shrink, reducing node capacitances and switching frequencies, or even use of advanced material technology. For the most part though, these approaches deliver only incremental improvements.

The never-ending need for low-power circuits is now motivating designers to explore new options in circuit design. What are some of the options currently on the table and will they provide the answer to the ongoing low-power dilemma? Let’s take a closer look.

Designing for low power

As is common in the electronics industry, when designers hit a wall—some technical challenge for which they have no clear cut solution—one of the initial responses is to re-examine existing ideas and technology. Often, a technology that may have been developed years or even decades earlier, for an altogether other purpose, can be repurposed in a creative new way to solve the challenge. In many ways, that seems to be what’s happening for modern CMOS circuit design. The industry now finds itself taking a fresh look at two decades-old circuit styles: adiabatic and asynchronous. Both approaches now promise to offer a possible solution to low-power circuit design.

Adiabatic Logic

Adiabatic or energy-recovery circuits use reversible logic to conserve energy. They achieve low energy dissipation by restricting current so that it flows across a device with very low voltage drop and by recycling (reusing) the energy stored on the device’s capacitors. This approach differs dramatically from CMOS circuits, which dissipate energy during switching.

There are two basic types of adiabatic circuits, fully adiabiatic and quasi adiabatic (See figure 1). With fully adiabatic circuits, charge from a discharging capacitor is used to charge the capacitance from the next stage. While these circuits allow the designer to obtain asymptotically zero energy (losing energy only due to the leakage currents through non-ideal switches), that benefit comes at the cost of substantial design complexity.


Figure 1. Examples of fully adiabatic logic families include split level charge recovery logic (pictured on the left) and reversible energy recovery logic. Examples of quasi-adiabatic logic families include pass-transistor adiabatic logic, latched pass-transistor adiabatic logic, and the 2N-2P family (pictured on the right). Graphic courtesy of M Tech (ICT), Dhirubhai Ambani Institute of Information and Communication Technology.

Quasi-adiabatic circuits are not nearly as complex, boasting a simpler architecture (e.g., adiabatic charging and discharging) and power clock system, which makes them much more practical for today’s electronic systems. These circuits also feature minimum energy loss that is typically proportional to the capacitance driven and the square of the threshold voltage. Popular quasi-adiabatic topologies include the PAL circuit which operates with a two-phase sinusoidal power clock and the TSEL circuit with its single-phase power clock.

While adiabatic design is an energy efficient way of designing for low-power circuits, there are a few tips which should be considered when designing adiabatic circuits. They include:

  • Never use diodes.
  • Never turn on a transistor when a significant potential difference exists between its source and drain.
  • Never turn off a transistor when there is a nonzero current flowing through its channel.
  • Employ a design style that accommodates mostly reversible logic.
  • Do not over constrain the design. Make sure it is flexible enough to express the most asymptotically-efficient hardware algorithms possible.

Asynchronous Circuit Design

Like adiabatic circuits, asynchronous circuits are a promising technology for low-power, highly modular digital circuits. In contrast to synchronous circuits which operate according to clock timing signals, asynchronous circuits use handshaking between their components (operating virtually autonomously) to perform all necessary synchronization, communication and sequencing of operations (Figure 2).


Figure 2. Shown here is an example of asynchronous operation. Graphic courtesy of Nanyang Technological University.

Asynchronous circuits fall into a number of different classes, each offering different advantages. A prime example is the quasi delay-insensitive circuit—a class of asynchronous circuits that are invariant to the delays of the circuit’s wires or elements (except to assume that certain fanouts are isochronic). One of the key advantages of this circuit is its low power consumption stemming from its elimination of clock drivers and the fact that no transistor ever transitions unless it’s performing a useful computation. A key disadvantage of this circuitry is that the asynchronous control logic designed to implement the handshaking may represent an overhead in terms of silicon area and circuit speed.

Despite the low-power consumption advantage of the asynchronous circuit, its use in electronic systems is today hampered by a number of factors. The chief problem is that electronic design automation (EDA) tools and methodologies for asynchronous design have been few and far between. There is also a lack of commercial tools for testing and test vector generation.

One solution to this issue comes from the European-based startup Tiempo (www.tiempo-ic.com). At the upcoming Design Automation Conference in San Francisco, July 27 – 30, the company will demonstrate the industry’s first synthesis tool for asynchronous logic. According to Tiempo, the Asynchronous Circuit Compiler (ACC) tool can be inserted into a standard design flow. It generates asynchronous and delay-insensitive circuits from a model written in a standard hardware description language. The tool takes as input a description of the circuit in the form of a transaction-level model. It outputs a generated gate-level netlist in standard Verilog format.


Demand for low-power designs will likely not abate anytime soon. Classical techniques can be used to address this demand, but with their incremental results, designers will need to explore other options. Adiabatic and asynchronous design styles now offer designers an alternate solution to dealing with the low-power dilemma. While not yet widely accepted, these design styles are gaining in popularity and in some cases, even finding support from EDA tools. As energy dissipation moves toward overwhelming all other design concerns, design styles like these will be critical to providing the energy efficiency that today’s electronic system require.

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