Experts At The Table: IP Subsystems

Second of two parts: Changing the cost of entry; questions about innovation; anticipating yield; different levels of partnerships.


By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that conversation, which took place before a live audience at the Semico Impact Conference.

SMD: Do subsystems limit the number of players that can compete in the market by raising the cost of entry?
Kablanian: Absolutely. The integrated device manufacturers and large chipmakers have been able to do this integration for years. It includes everyone from software to architect to RTL designer, physical library providers to the fab. They have the whole vertical know-how. For a small company to do this is almost impossible. Naturally it will limit the number of companies doing this, and it will force consolidation among a few players.
Gianfagna: You’ll have to have more investment and more vertical knowledge, and that in general will result in a better deliverable. I don’t think it will limit innovation, though. The market resists being homogenized. Differentiation will continue at a higher level of abstraction.

SMD: Software is a subsystem, right?
Gianfagna: It is.
Roddy: There was a time when you could count 500-plus IP providers. But if there are 3,000 to 5,000 design starts, you can’t have 500 IP providers. They’re all going to wind up with five customers. That doesn’t work. But there can be 30 to 50 IP providers.

SMD: Both of the big foundries have done testing of IP. Will that continue with subsystems?
Meyer: You have to look at that by technology node. The closer you are to the bleeding edge of technology the more expensive that investment is. There you’re going to limit the number of partners. You have to do that because you need solutions as early as possible for existence proof of that technology node. We work very hard on that, and we do that with guys who know what they’re doing and who are capable of providing a level of support at that design level. It’s not just throwing it over the wall and getting IP. The IC integrator has to be involved to do that successfully. But as we start moving away from the bleeding edge, we want to work with innovative companies doing things like power management at 1.3 micron or even 65nm. With embedded and non-volatile we look to work with those companies.
Kablanian: There is room for the foundries to adopt new IP and take some risks. That has not been done.
Meyer: A lot of what we’re doing is anticipating yields. A lot of our focus is on working with companies like Cadence and Synopsys and Mentor on yield enhancement, and we’re working with system providers to understand how that IP will work in silicon. We think our customers get a lot more of an advantage working in those areas, like DFM, as opposed to the system-level aspect. That’s why you can come in with a customer who really understands the value of what you’re doing.

SMD: One of the great advantages of stacking die is that you don’t necessarily need to worry about developing IP at the latest process node. What does that mean for subsystems?
Roddy: If it becomes widespread then the economics of the value chain will change. That’s a dramatically different business model because the IP provider essentially is a contractual silicon provider. They might sell you a 50-cent sliver of silicon that you’re integrating, which is dramatically different business structure. The analog IP provider works to validate with the global partner. You could be sitting back at quarter micron for your analog and your memory might be at 14nm.
Gianfagna: There is certainly more predictability.
Roddy: It adds much more opportunity for the analog part, which has less flexibility because they have so many process-specific attributes. If you get it right, then there will be an emphasis on keeping it in that process.
Gianfagna: If you get it right for subsystems, you can make the same argument.
Roddy: You can still validate a piece of silicon with the proper interface. That may be the next evolution.

SMD: Subsystems aren’t a new concept. It’s been done at the board level for decades. But have we gotten to the point where designers are willing to let others create and verify these subsystems?
Gianfagna: It’s no longer a question of who designs the best circuit. It’s who integrates it the best.
Roddy: There are a handful of companies that still do their own libraries, but the vast majority do not. The vast majority doing SoC design are no longer providing all of the pieces, but they are working with vendors to optimize blocks wherever they can.

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