Experts At The Table: Multi-Foundry Strategies

Last of three parts: The impact of 3D stacking and 3D structures; business changes and commoditization; competitive concerns; multisourcing at the leading edge.


By Ed Sperling
Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president of marketing at Kilopass. What follows are excerpts of that conversation.

SMD: Where does 3D stacking fit into all of this?
Ng: There are limitations with 3D IC with regards to performance. It may be a possible solution for some applications, but for things that require very high performance 3D IC isn’t a solution.
Hong: I don’t agree with that. It’s hard to say whether a vertical wire or a horizontal wire is faster.
Murphy: It’s really about how to get wider access to memory.
Smith: We have a number of customers doing work in that area. From all the presentations I’ve seen, one of the things they stress is that it’s better for performance and much better for power consumption.
Buehler-Garcia: But it’s not about being faster. It’s wider.
Murphy: If you analyze computing systems, when you get high latency to memory it’s very difficult to solve because the power consumption through that I/O exchange of energy is so high. From what I see, 3D IC is primarily for the memory interface. That’s really where it’s going to shine.

SMD: Why isn’t everyone in agreement here on the performance of stacked die?
Buehler-Garcia: There are different kinds of performance. The clock performance on a chip may not improve. You can run 2GHz, but if you can’t get that to the bus it doesn’t matter.
Murphy: It doesn’t matter how fast the CPU is if it’s waiting.
Ng: And you won’t see a CPU design leverage that.
Murphy: No, it’s going to be subsystem.
Ng: If you take a look at most of the microprocessor designs today, they certainly are big and fast.
Buehler-Garcia: It’s the rest of the design that isn’t as fast.
Murphy: There’s a lot of depth of cache right now. One thing that Wide I/O could do is move that cache off the processor.
Buehler-Garcia: And then you can buy the memory from a company that builds memory for a living, rather than trying to make it out of bulk CMOS logic.

SMD: Then your multisourcing becomes whoever has this stuff available, right?
Buehler-Garcia: That’s correct.
Ng: It should make the other pieces like the memory die a commodity.
Buehler-Garcia: It doesn’t make it easier, but it does add another variable to consider.
Murphy: It also comes back to who can afford it and get access to it.
Ng: At this point, it’s who can drive something that’s actually a solution. There’s still a lot of work to be done to make a 3D IC accessible to the masses.
Buehler-Garcia: This also may open up a different business model for companies like Kilopass. Right now it’s IP for SoCs. But customers may be asking for a full chip that can be put into a 3D IC.
Hong: That’s a possibility, but right now that’s not where our market is. Being embedded is where we add value.
Ng: The area that Kilopass’ IP takes up is quite small, too. For large memories, it makes a lot more sense.

SMD: Isn’t it the same for a piece of logic, too? If that’s not your competency, you can buy the best one for your needs.
Buehler-Garcia: And that’s what FPGA vendors provide. If you don’t want to build it you can buy it. It depends on your business model. Are you an ASIC vendor or a fabless chip house?
Murphy: If you want to take on the cost and the risk of doing 3D IC, you want to get a significant advantage for doing that. It’s a business model change. And even if you don’t buy the memory, you may want to buy a memory controller and put that in the stack.
Buehler-Garcia: The unanswered question is who’s going to integrate all of this. There’s a first and last TSV discussion. A major foundry is going to have to integrate that and then send it to another foundry, which they’re not going to be real thrilled about. But if it’s an assembly house, that’s okay because they’ve had a relationship for the past 10 years.

SMD: The politics in this industry are getting very interesting.
Buehler-Garcia: Yes, and when you talk about logic-on-logic and you’ve got a place-and-route tool between two different technologies, that gets interesting.
Murphy: And with verification this will get even more interesting.
Buehler-Garcia: Exactly. And the integration of two different process nodes will be even harder.
Murphy: So if your TSV is in the wrong place, do you re-spin four chips instead of just one?

SMD: What happens with yield on multiple sources? Does it make it harder to move from one foundry to another?
Murphy: Restrictive design rules are a way to allow the design flow to comprehend the design rule manual, more in the actual flow than an after-check. The reason we have hotspot checking, for example, is it’s a reasonable tradeoff to do it post-processing than in the flow. But there are differences now that cause us to make changes in our tools for different foundries. It isn’t going to get any easier.
Buehler-Garcia: For a foundry you may have 20 companies coming in chasing one socket and each one has a different idea how to do that. And you’re supposed to write one set of rules to cover that. They all get negotiated and tweaked a little bit. But the tools have to handle multiple decks, multiple kits and make the tradeoffs. If you’re a sharp design team, you can optimize your design within those rules and get much better yield than other teams competing for that design win. That’s been happening since 0.25 micron.
Ng: At the leading edge it’s far more difficult to multisource. There’s a certain overlap of the recommended rules because there’s only so many equipment vendors offering equipment to leading-edge manufacturing. But that isn’t the only source of the recommended or restrictive rules. Another source is the OPC recipe. If the equipment set on the back end is different between different manufacturers, you may yield fine with a certain manufacturer and poor with the same shapes for another manufacturer. When manufacturers are distinctly different it makes it harder for customers. Even among those of us who are trying to align on a platform that’s difficult. But we do it because there are large customers counting on us. At the leading edge, though, it’s getting more difficult to source the same design without re-design, and there isn’t the time to re-design.

SMD: Does it get more difficult as we move to FinFETS and/or ETSOI?
Ng: Absolutely. The splinter of technology choices will make it much more difficult. If one uses FinFETS at 22nm and another puts it off until 14nm, it becomes more difficult. But each manufacturer is doing it because of what they feel is a different value to the customer.
Murphy: The companies that will have the most difficult time will be the hard IP vendors.
Buehler-Garcia: Particularly the star hard IP.
Hong: It is incredibly challenging. Going to high k/metal gate with gate first or gate last, the design as well as the qualification and characterization are difficult to leverage.
Ng: It’s going to get more expensive from the IP side, too, because if they’re doing a one-off for everyone’s process it will be more challenging. With FinFETs even the physical design tools are going to be impacted.
Buehler-Garcia: If you have a different variation, can you cover it with the same algorithm? It’s breaking down the expertise in the flow. How do you maintain all the decks for all the nodes and all the variations? For 20nm, we’re on the 20th version of the deck.
Murphy: And you need the IP vendors to determine which IP is required when. We’re going through that at Cadence.
Buehler-Garcia: The approach is, ‘With no frozen PDKs and no frozen decks, let’s take a shot.’
Smith: It’s a target that’s moving all the time. And, oh by the way, kids want that cool device for Christmas. They don’t care if it’s 20nm.
Ng: The applications driving the advanced technology these days are consumer—at a very low cost with a short market window. The ramps in the fabs go up quickly. If you’re not able to ramp in that given timeline, that potential customer has lost hundreds of millions of dollars of revenue. It’s a big risk.
Murphy: The other market besides consumer is embedded controllers. Motor controls have to be analog/mixed signal. Is that a business model? Does the 3D IC open a business model to help that market develop quickly vs. pure analog?

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