Experts At The Table: Stacked Die And The Supply Chain

First of three parts: The growing need for standards; questions about cost and business relationships; new terminology; who’s responsible when something goes wrong.

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By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis at Tessera; and Sashi Movva, strategic sourcing specialist at Qualcomm. What follows are excerpts of that conversation.

SMD: What are the big challenges in 2.5D and 3D?
Pateras: From a test perspective, what we need are more standards. How do you get data from one device to the next? How do you create tests that span more than one device? That means these devices have to be compatible in how they communicate test information and how they deal with embedded test capabilities. The EDA players need to get together and support similar test capabilities.
DeLaCruz: The challenge that was covered first was the technology. Where there hasn’t been a lot of attention is on the supply chain. Everyone has nice solutions, but the interconnect technologies are all different. So if you want to source a memory from one provider, a PLL from someone else, a voltage regulator from someone else, when you connect these things together they may all be different because everyone has their preferred solution. You need standards in test, but you also need them in interconnect technology to assemble it in the same location. The assembly guys are reluctant to give out design rules because they want to see what the prevailing trends are. If there are too many different styles of interconnect, it may be too difficult to handle—at least for the general ASIC market. On the other hand, you may have companies that are more vertically integrated and which have a hand in each of the chips that is in there. They can more easily put them together and design them the same way. But when they come from multiple locations, compatibility is going to be a major obstacle.
Woychik: What’s going to be very important with 2.5D and 3D is coming up with a fully integrated solution. What’s happening is there is a lot of expertise in one area, such as TSV formation at the wafer level. There’s a lot of work in test. But how do you bring all of these elements together to come up with a fully functional 3D IC device? When you look at it generically, 2.5D and 3D are very similar. The difference is that 3D is a functional device while 2.5D is a passive device. At the same time, you’re going to have to bring all these elements together to provide a total solution. In the industry we’ve become very fragmented over the last 10 to 20 years. This is going to really drive a blending of the IC fab with the packaging house to provide this solution. Once this happens, there ares going to be a lot of people who say they need it.
Baldwin: It starts with nomenclature. There are new terms that need to be created—things like test elevators and what you call the ball that sits on top of the through-silicon via. Is that different from a bump? We talk about tools issues. One of them is 3D extraction. We already have 3D extraction, but now we’re talking about to another die in the stack. Is that 3.5D? In thermal issues, if you’re looking at a thermal gradient that goes vertically through a die stack as opposed to a horizontal one, there are no words to describe these new issues and to work through with the customer how we’re going to solve these problems. A packaging house put together a presentation for a 10-die vertical stack for us, and they had all identical-sized die with perfectly aligned through-silicon vias. It was clear we don’t have the technology to build that today.
Movva: The technology is not ready. The standards are still to be decided. But the industry has come a long way in the past couple of years. There have been prototype lines set up by the foundries and at OSATs. Test methods have been developed and reliability has been improved. These are no longer the obstacles for 2.5D and 3D. The challenges we see are twofold. One is the cost. The other involves the business models. With any new technology there is a learning curve, so costs are higher. But what concerns us is that some of the risk elements of the new technology are being added as a premium to the price. Those come from the technical uncertainty and risk, and also the business model uncertainty and risk in terms of who owns the different processes. That is a major concern.

SMD: And what has to change with the business models?
Movva: When flip-chip was introduced there was a new technology called bumping. That technology got resolved. But with 2.5D and 3D, who owns the new process fabs? Is it a foundry process? Or is it an OSAT process? Where does the handoff happen? Those are big challenges, and they need to be resolved for this technology to take off.

SMD: One of the great advantages of this model, at least in theory, is time to market with customized solutions. But is it going to happen smoothly and will all the pieces go together?
Woychik: What’s really driving this is a fundamental need to address Wide I/O. At the same time, with Wide I/O, you have memory and logic. It’s going to have to drive the standards, and the right now standards are immature. They need to be developed. There will be standards for design, TSVs, packaging and thermal issues. And how is this going to get manufactured from the fab to the packaging house? If you look at packaging, it has a history of being an afterthought. The fabs would hand it over the fence to the packaging group and the two never talked. About 10 years ago, with the introduction of copper and low k, the foundries began to work with the packaging houses. 3D IC will be much more intensive. There will be a blending of the fab and the packaging house. And as we get into 3D standards and protocols, the blending of the two worlds will be necessary to pull this off.

SMD: How will the industry need to change to deal with this?
Woychik: I started my career at IBM, which was a fully integrated company. The industry disaggregated after that. 3D IC will drive re-integration, but it’s going to be in a new form.
Pateras: We’re viewing 3D very much as an extension of what we do in 2D. We’ve been combining IP from different vendors in 2D and putting them onto the same chip. With 3D, instead of putting this all on the same chip you’re putting it on separate die. What adds more complexity is whether you put memory on the same die vs. on a separate die, but from a test perspective it’s very similar. That’s not the same if you take two logic cores and combine them into the same design. You still need to test the same things using the same techniques—scan chains, isolation. But when you do that on two different die all bets are off because you may not have access to one of the die from an automation point of view.

SMD: But what do you do with two known good die that don’t work together right? Pateras: When it comes to memory on logic we can deal with the interface because we understand what memory interfaces look like, no matter who is creating the memory. But if you look at logic on logic, these interfaces are completely arbitrary. If you don’t have control of those interfaces, testing becomes much more difficult.

SMD: What changes in terms of responsibility?
DeLaCruz: Right now there’s a very big hole in the industry. We refer to individual die as tiles. The IP vendors are in the business of selling IP. They’re not in the business of supporting die sales or taking care of test or test methodology. People doing package devices now also are not set up for die sales. It’s a completely different business in terms of test, test infrastructure and yield management. On the other side are the wafer foundries. Will they step in and provide these tiles? It’s not their business. Nor is it for the assembly houses. There’s a gap right now, and that’s where we’re focusing our efforts. We plan to provide of menu of these tiles. By doing this, we’ll be able to provide a standard by default because we’ve done all of these devices by ourselves. It will make things fall into place and make sure that these devices will be interoperable. Even from a test standpoint, you’re going to have one common device with a certain amount of test compression, but you have to pin out the other devices to be able to accept that level of test compression from that first die. If you’re sourcing these die from multiple sources, the chances of them being set up right to make this work is almost non-existent. It’s like dropping a coin and expecting it to land on its side.