Experts At The Table: Stacked Die Reality Check

By Ed Sperling
Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of marketing for advanced packaging and nanotechnology at Ultratech. What follows are excerpts of that conversation.

SMD: What are the main problems looming in 3D-IC from a manufacturing and design standpoint?
Ranjan: On the demand side there’s been a lot of talk, but customers have not committed to this yet. The reason is there are some supply chain issues with regard to who does what—who supplies memory, who supplies logic, who integrates everything, who’s responsible for yield, who does microbumping and who does test. That’s a big problem to solve. There are also problems on the tools side with respect to thermal management when you are putting logic plus memory together. There are no good 3D tools out there that can help you look through these issues. If you’re just doing memory plus memory integration it’s easier, but if you’re doing mixed-device convergence that’s a big problem.
Smith: From what I’ve seen, all of the partners in the ecosystem are doing their part to prepare for true 3D-IC—stacking die one on top of another. The foundries are preparing the manufacturing. The equipment guys have already got their equipment out there and it’s being installed in the fabs today. A lot of people point fingers to EDA because we don’t innovate in the usual way. What we’re really doing is automating existing processes. We’re waiting for the demand side to pick up. When we look at the real companies doing 3D-IC, there are very few doing active designs. Most is early research and prototyping, testing the manufacturing process, testing the reliability of the stacking mechanisms, looking at the electrical characteristics, and so on. We have done quite a lot of work in providing the basic toolkit that’s necessary for any design company to start that work. Most of the companies today are working on silicon interposer technologies, which is an intermediate point. The other thing a lot of people complain about is standards. Those typically come either from proprietary formats or languages that become popular, such as SystemVerilog. It’s a little premature to look at EDA interface standards for 3D-IC because there isn’t enough experience. The things being done today are fairly simplistic, anyway, so they won’t be applicable to a wide variety of customers.

SMD: How about the thermal tools?
Smith: From a technical standpoint, thermal is an issue. The analysis tools are too low in capacity or not high enough in capacity. But from an EDA standpoint there also isn’t enough business there to warrant an all-out attack with new tools. But I don’t see any major technical challenges.
Matthias: The future is very bright in terms of 3D IC. The train is moving and it’s accelerating. About five to seven years ago there were a lot of questions about how you manufacture a 3D stack. There was a question about how do unit processes interact with each other. At this point, there are no unsolved issues in manufacturing. There are baseline processes that work. We’re now in the phase where we’re really trying to make the manufacturing smarter. We started with the idea of doing one chip at a time, then think about how to stack them. Now we’re thinking it’s better to stack them first, then do the processing on the first layer and then the second layer, and then do a compression bond on top of that and do the bumping later on. There is a move to get into more intelligent manufacturing integration schemes. There’s confidence in the industry that we can actually manufacture 3D-ICs. Five years ago, it was only the MEMS companies, which are obscure. Today everyone knows you can get a yielding device. Now it’s a question of whether this is the best approach for a product. Progress is accelerating, though.
Patel: I totally agree. The unit processes are in place. The key is maturity now. We all need to work through the supply chain. We need to do the front end and hand it off to the OSATs, who are experts in handling the wafer thinning and backside processing. What we are doing today is working through many wrinkles and pushing through the lots, working through the supply chain to gain maturity and get higher yield. For volume manufacturing you need to define the design parameters and design processing windows.

SMD: Have we gotten beyond the test chips?
Patel: We are still in a test-chip phase. We do have some initial product tests, but there are many issues we need to work through such as how do you handle thin wafers once they are shipped, how do you test them and ensure known good dies, and how do you ship memory wafers. If those wafers are packaged, that’s not a problem. If they’re not, how do you ensure the known good die? Also, with memory, the key integration is logic plus memory. In that case, the co-design of different die comes into the picture. Also, do you adopt for the 3D memory standard Wide I/O 1, Wide I/O 2, and in 2.5D do you use Wide I/O memory or high bandwidth memory? Those are things we need to fold into manufacturing, along with robustness. We need to work through the entire supply chain—memory, EDA and design IP. The unit processes of filling the vias, backside thinning—each piece has been individually perfected. Now the time comes to put it into practice and make it a robust practice.
Pateras: When it comes to test, there are a number of different areas. Clearly 2.5D is being used a lot. We’re seeing a lot of need for testing memory stacks with an interposer on an SoC. It’s not quite mainstream. We’re seeing some customers moving to vertical stacks on an SoC this year. The testing problem there is well understood. The JEDEC standard is well defined, whether it’s Wide I/O 1 or 2. The JEDEC memories have scan chains in them, which is one way of testing the memories and the SoC. You can use memory BiST. We’re seeing this implemented by many different customers. There’s less of a need for standardization there because you’re generally just testing a memory bus. The bigger challenge is with stacked logic die. We have not yet seen that. There are a number of issues there. One is the known-good die problem. How do you ensure you’re getting good die when you stack them together? With memory it’s easier, because there’s a robust testing methodology for bare memory die. With bare logic die, particularly with heterogeneous parts, the quality of those parts comes into question. And if you stack them together, you may have a yield issue.

SMD: How about when we actually stack the die together in a 3D-IC?
Pateras: That’s an even bigger problem. How do you access them in the stack? You can’t access those I/Os from the outside. You need to go through TSVs, so you need a way of being able to access those die. And if they’re heterogeneous, you really need some kind of standardization. There are some existing test standards, but these are not good enough for a vertical stack. This is still not solved. There are some proprietary solutions. IMEC has developed one. We have developed one. But if you want to bring parts together from different sources, you need standardization. The 1838 working group is addressing that, but progress is slow. Once the standard is in place, then the problem is much more tractable. Right now it’s divide and conquer. The stress of the TSVs may result in changes in timing characteristics of the transistors around the TSVs.

SMD: Is the business case for stacking compelling yet? For a long time everyone was saying stacking is too expensive, but 20nm or 14nm chips are expensive, too.
Ranjan: It’s a cost-to-performance issue. It depends on what products you’re manufacturing and what the lifecycle is. I don’t believe the costs have been well characterized yet. If you’re running 22nm, it becomes very complex very quickly—what kind of wafers, what kind of yield, what kind of utilization. How do you do apples-to-apples comparisons with TSVs? In general, going down Moore’s Law is very expensive, so companies will take a look at alternative solutions. Packaging may enable this cost-performance tradeoff. At what point does it become attractive? That isn’t well understood right now, especially for TSVs. With 2.5D, we see a lot of traction at 28nm. Companies are in production today, although in limited quantities. A lot of other device companies are lining up at foundries for 2.5D solutions. But with 3D, we don’t see that yet. My personal opinion is that real 3D won’t happen in any sort of meaningful volume until 14nm.
Smith: This is all based on ROI and economics, but we’re seeing some companies moving to stacking where they have control overall the aspects of the integration. If you have the economics figured out, you still have the ecosystem issue. The supply chain is not mature yet. We do see IDMs that have the manufacturing moving forward, though.