Experts At The Table: Billion-Gate Design Challenges

By Ed Sperling
Low-Power Engineering sat down to discuss billion-gate design challenges with Charles Janac, CEO of Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. What follows are excerpts of that discussion.

LPE: If you don’t look at this as 1 billion gates, but instead look at it from the standpoint of subsystems, is it easier to justify from a business standpoint?
Browne: Yes because you know these customers because you’re tier one, two or three in this segment and you know what to put together. You may be nowhere in another segment. So here you do something original. Here you try something new.
Rajendiran: There is a difference between a derivative and a variant. You can start out with one chip, do a re-spin and get a derivative. A variant is where you start out with a big system and then that hardware is given to all the divisions in the company. Each product line comes up with what to do to create a variant, mostly in software.
Janac: Is a variant a software re-spin?
Rajendiran: That’s what we’re seeing. It’s like a superset.
Browne: We’ve seen that in a lot of companies, too. You don’t know what you need for a particular market so you create a superset.
Rajendiran: Not only don’t you know what you need, but the markets are changing. You don’t have time to figure it out. Are you really going to do a billion-gate design from scratch? Probably not. When you do a new chip the traditional defect density model tells you that your yield is low. So can you easily take what you have and do it in four chips? This isn’t the traditional way of doing integration. If I can make them into four chips and tie them together with 2.5D, then you get better yield.
Browne: Or can company ‘A’ race to market with multiple chips. If not, then the slow and steady guy may win. How far do you jump out ahead before it’s off a cliff?

LPE: On a multicore/many-core implementation, are these core sizes becoming more heterogeneous?
Throndson: There’s definitely a lot more interest in that area. One of the more popular configurations in the application processor space for these Internet-connected applications is in mobile or the digital home. It may have floating point or no floating point, which can affect a significant chunk of the core size. That works on other features, too.
Browne: It’s hardware vs. software.
Throndson: Yes. Software needs to be a little bit more aware of where those dedicated resources exist, but that’s a manageable problem. It definitely helps to save power and area, though.

LPE: EDA traditionally has been one size fits all. Are the tools moving in those directions.
Baker: System-level change based on applications is very interesting. Right now we’re in a vertical space and there are functional verification, custom design and digital implementation areas. All of us are trying to find ways to automate the process by abstracting it up a level to get to an answer more quickly. The EDA industry needs to make tradeoffs on area, power and cost so we can add productivity to the design teams. Everyone is working on that now.

LPE: It used to be a tradeoff between power and performance. Is performance no longer an issue?
Janac: It depends on the market. If you’re in DTV and you’re operating on a 25% or 30% gross margin, the die size becomes very important because it’s so cost-sensitive. If you’re in a high-margin base station, area is less important. It’s all performance. It depends on the market. But in the billion-gate chip, the big concern will be risk. People get fired for being late and for quality problems.
Browne: But risk is different things for different people. Samsung’s president said his company will be using TSVs in 2013. There are ‘Haves’ and ‘Have Nots.’ If you need to get there first you’re going to have a different risk profile than if you’re a follower. And it’s a whole continuum.
Janac: But whoever is in charge of the Samsung TSV chip is going to get fired if he doesn’t get there by 2013. He’s got to be very cognizant of the implementation risk he’s going to take to do the project.
Browne: And someone else will get fired if the factory isn’t full.
Janac: But the guys who create the design don’t get fired if the factory isn’t full. They get fired for not delivering on time, on scope and with quality.

LPE: Will we be able to get these chips out the door on time with a billion gates?
Browne: We have to improve on quality at the same rate as we improve on dealing with complexity. It’s a marathon race, not a sprint.
Rajendiran: Some companies can afford to take a huge risk. Hopefully other companies will be smarter about how they approach this. It is important to differentiate by market. But there are more ways to get there than just by following Moore’s Law. We don’t have billions of dollars to write off.

LPE: Isn’t some of this about getting more granular in the design?
Janac: The key in a billion-gate design is how you manage the partitioning and the IP re-use. You need to understand the risk of not redoing the IP, as well as the risk of redoing it.
Browne: It’s all about how it works in the system. The guy with more understanding that will have the ability to reuse more cleverly.
Baker: Certain companies will rise and succeed because they’ve built the knowledge base internally.

LPE: What happens on the manufacturing side? How do you manage yield issues?
Rajendiran: At any process node it’s the same. One thing the better foundries do is apply their learning to get to a better level of yield. The more chips you do, the more expertise you have, the better you get. We’ve done it and learned it with in-house expertise. You have the building blocks, the tools and the expertise. That’s what sets one company apart from another. Anyone can buy the tools, but can the produce it?