Experts At The Table: Concurrent Design

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion.

LPE: Is concurrent design strategic—meaning is it done at the architectural level—or is it tactical across all phases of the design?
Gianfagna: You need both. That’s the bad news.
Brambilla: The tactical portion of it is possible today, but I have no idea how to do it strategically. Nobody is writing machine code anymore. It’s not efficient. If someone wrote Windows in machine code it would be a 1 megabyte executable instead of a 1 terabyte executable.
Janac: It would never get done. At Cadence for years we were trying to catch Calma, which was the leader in layout. They had 4 megabytes of RAM and they were running on a 16-bit minicomputer. And they were more efficient until the Sun 260 generation, which had 256 megabytes of memory, but Calma could never get off the Eclipse. You’re trading off use and configurability vs. time to market. If your cost is too high and you’re too inefficient you will not be competitive. On the other hand if you’re too efficient and make the last optimization of hardware you’ll never get done and you’ll lose the market.

LPE: Going forward, if time to market and standardized IP are essential, do we have the expertise to do concurrent design?
Brambilla: With different IPs, you have the problem of porting. You may have a piece of IP that works beautifully on a 65nm process. TSMC’s process will not be that different from ST’s, but you still have to port it to make it work. That’s a problem, because you have to face all the implementation steps. Today we don’t have the tactical portion done well enough. People need to know about certain coding styles or electromigration issues. That’s the tactical portion. The strategic portion is what you can do so people don’t have to be concerned about it. If we need to distribute a bus, we have to almost do the buffers by hand. There will always be certain areas where you need the expertise of people who have done it. But I’d rather have someone who understands what areas need to be addressed rather than have to deal with every portion of the design.
Janac: When you want to synthesize the network of a bus you don’t want to do it by hand.
Brambilla: Or if I know that is a peculiarity, I can deal with that, as well.
Janac: But if you look at the strategy of Synospys, they’re on the right track. They are packaging the IP, and someday they’ll package it with their tools so they wind up with a system where you can do that kind of analysis at the architectural level. But it’s going to take a combination of tools and IP. When you’re at SystemC level, how good is that analysis going to be? It won’t be very good unless it’s dealing with the USB 3.0 model or the network-on-chip model or the actual ARM model. You’d better have those models and they better come directly from the IP.
Brambilla: If I go to a vendor and they have the 32 L and the 32 G, which one do I choose? I have to make a decision at that level because if I choose the wrong node I might not be able to mix them. There will be vendors that will offer an L and G process and others that will offer an LG. I can kill myself with leakage or performance.
Gianfagna: We’re describing an interesting change. Picture a funnel, which is wide at the top and narrow at the bottom. In the bottom half, concurrent design is so hard in terms of balancing the physical effects, the variability and the integration effects that there are a small number of companies capable of dealing with that and build a chip that yields and works. But how does that small group of companies serve what’s above them in the funnel? The answer is some number of architectures that work, and then add in enough programmability and variability. The bottom of the funnel is a small number of companies that understand how to go from gate architecture to silicon. What’s above the funnel today—a large number of fabless semiconductor companies—they go away. What those people do then is to figure out how to add their own customization, whether it’s in the form of FPGA programming files or interesting ways to build a 3D stack and software. These increasingly will be software companies. The hardware will be an assumed thing.
Janac: The problem is that the top of the funnel is feeding junk into the bottom of the funnel. How do you get that knowledge from those experts into the front end of the cycle so you don’t get junk?
DeLaCruz: Yes, by the time they get it it’s too difficult to change anything. There are tradeoffs we make on IP selection. Sometimes high-end IP has a pre-set bump assignment on it, such as SerDes. That will dictate what stack you can use. Maybe going to a different performance can change the economics. There’s no way an EDA company can figure out what those tradeoffs are going to be. Or if you make other tradeoffs like increasing the amount of capacitance on a chip so you don’t have to put that capacitance in the package or on the PCB. There’s no one tool that considers all those different things. Or if I make this one tradeoff my power will go down, but I may be going to a process that has more leakage. These are the kinds of tradeoffs you need to make very early on. Do you go system on chip, network on chip or system in package? There are different tradeoffs. It’s a combination of expertise and resources.
Brambilla: I totally agree. To solve that you don’t need the packaging expert. You need someone with a vision of the final device. When we start we need to know this thing has to go on a PCB. If I use a package that’s too small it may save you $1 on the package and cost you $20 more on the board.
Gianfagna: The system-level engineers and architects are the guys at the top of the funnel. I would argue those people can’t worry about all the issues we’re talking about. They’ve picked a package and a set of silicon and a set of programmability, and now they’re trying to figure out how to use that effectively. That might be programming an FPGA layer in a stack. It might be choosing a different memory because there are a few that are pre-qualified. And then there’s a lot of application software that needs to be run on this. Those are the decisions that are made at the top of the funnel. The minute you start factoring in the technology node, you can’t get there.
Brambilla: There are limits to that.
Janac: People are starting to figure out the software and functionality use cases, and then they’re starting to figure out the hardware that supports those use cases.