Experts At The Table: Concurrent Design

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion.

LPE: What is concurrent design and how has the definition changed?
DeLaCruz: This is a legacy we created for ourselves because physical design teams can operate separately from CAD tool developers and packaging and everyone throws what they’ve finished over the wall. Concurrent design is a way of undoing the damage we’ve driven into our culture. We can do this by creating CAD tools that allow concurrent work on the same thing. Cadence, Synopsys and Mentor are all trying to create tools for this. Another way of doing this is by getting your people to talk together more effectively. That’s difficult because people have been told they should work in different departments, not talk to each other because things get messy that way and take too much time.
Gianfagna: There are two things that caused the problem. One is that we used to do things sequentially. You did placement, you did routing, and then you’d tweak the placement and timing would be closed and everyone would be happy. You can’t do that anymore. Now when you change placement you break timing. When you fix timing you mess up clock synchronization. When you fix clock synchronization you mess up power. And they’re all related. One breaks the other. So there’s a need to simultaneously optimize. Beyond that is an even bigger problem. The supply chain is now spread out. You’re dealing with a separate packaging company, a separate substrate company, and five or six IP developers.
Brambilla: There’s another level of complexity. My team does turnkey designs and ASICs. When it’s turnkey it’s easy. When it’s an ASIC you also have a huge separation between the customer doing the RTL and us doing the rest. There’s a big discontinuity. When people want to go to the next node, sometimes they’re approaching it with a software mentality and don’t realize that a forward loop becomes a million gates. Once upon a time we did software-hardware co-design. Now you have separate entities who say that’s your job and this is my job, and we have to cross-educate them.
Janac: You’re taking a serial design and that serial design has gotten longer, and now you’re trying to make it parallel. The parallelization of that process cuts the time. The answer is that you have to consciously create islands where this parallelization works and then have very well defined communication between those islands. Let’s take this problem of the RTL designer and physical layout separation. If the physical layout guys can get the constraints up front into the RTL, then the physical layout people will not get junk from the RTL designer. There needs to be a well-defined set of interfaces between those islands.

LPE: But this is all getting more complicated, right, and not just within a single block or subsystem? You have proximity effects because of density, you have electrostatic discharge issue, power issues, heat issues, software that may or may not work across the whole thing, and version-control issues on IP.
Janac: Within these islands you have to take into account an increasing number of constraints.
Gianfagna: We’re hearing it with timing constraints. The front-end guy needs to worry about timing constraints more. What we hear is that’s a back-end problem. It’s hard-wired into everyone’s brain that it’s a back-end issue, but that’s wrong. Is there a human issue here? As an industry we don’t have a great track record of changing quickly.
Janac: Atrenta had an advertising slogan that I liked, which is that timing closure begins above RTL. The earlier you solve some of these problems the cheaper it is to solve them.
Gianfagna: Intuitively that makes sense. When it comes down to the real world that isn’t always the case. People don’t always approach it that way.
Janac: But then their chips don’t come out. It’s hard to tell an RTL designer they have to worry about congestion. But if you give them a capability to eliminate that congestion, such as cutting wires in half, then they’ll use it. But if you tell someone they should speak French it’s not going to happen unless you teach them to speak French.
Brambilla: There are several issues here. I wish we could still work in islands. The islands are getting blurred, or they require more people from different functions to work in them.
Janac: You need to build bridges between the islands.
Brambilla: But you also need to populate those islands. They’re no longer homogeneous. We have started on 28nm devices. These are 17 x 17 or 18 x 18 mm. You’re talking in excess of 100 million gates for non-repeating logic. The graphics guys are doing 100 million gates but it’s copies of the same thing. There is still a problem of validation, but from a design point of view it requires a different amount of resources. When we’re doing a communication ASIC of 100 million gates, that’s all random logic. You have people putting 4x more gates in the same area with greater productivity. They don’t have time to worry about congestion. And they’re moving up, up, up in terms of higher-level coding languages. If I want to port to double the frequency I might have to change my bus width rather than just doubling the clock.
Gianfagna: That’s a microarchitecture change.
Brambilla: But you can’t do that in Verilog. At that point you’re talking to a software person or an algorithm person, not to a designer. Try to explain to that person what the structures are that can cause congestion. Sometimes I have trouble explaining memories to a designer. They don’t get it. There are Verilog designers who don’t understand what their Verilog becomes in gates. How do we ask them to be more proactive?
DeLaCruz: We’re victims of the way we used to be organized. I keep hearing this term ‘islands.’ I think it’s a big crutch. We’re just putting Band-Aids on this. These islands need to be moved. Within eSilicon, rather than the physical design team creating something that can cause problems with packaging, and packaging causing problems with PCB design, we moved the line. We overlap physical design significantly. The packaging team does floor planning, pad ring layout, and all the SSO operations on the die. By the time it’s gotten to packaging we know it’s done properly. All of our packaging personnel are mixed in with our physical design team. That’s blurring the line. The islands aren’t being kept separate. As we go to through-silicon vias, is that interconnect a packaging issue or a design issue? You can’t have the delineation anymore.
Janac: Why not give them the tools that isolate them from the complexity?
DeLaCruz: Let’s say you have a chip design that can be a certain die size, in round numbers 4 x 4. The physical design team wants to add more signals. If you go to 28nm, you’ve got all these signals and your die has to grow. They don’t know about all these things like silicon interposers, which would translate that 4 x 4mm die into an 8 x 8mm die.
Janac: You can have an interconnect that contains all the wires. Do you put all those wires on one die or on another die? You’re giving them the tools to deal with that.
DeLaCruz: You have to cross-train because 3D silicon is not a physical design issue. It’s a packaging issue. There’s a methodology in physical design. There’s an issue in packaging. It’s a little bit of each, and you can’t have different people doing each.
Janac: It’s a combination of training and methodology. You have to train your designers and tell them that a 3D toolkit is part of the methodology they have. And then you have to give them the tools to successfully implement their technology.
Gianfagna: You can come up with the tools. We in EDA can come up with the vision. But it doesn’t mean anything unless there’s a mandate from the top down that this is the way things are going to work.