Experts At The Table: ESL And Low Power

Second of three parts: Power becomes one of the principal variables in design.


Low-Power Design sat down with Walter Ng, senior director of platform alliances at Chartered Semiconductor; Brani Buric, executive vice president of sales and marketing at Virage Logic; John Sanguinetti, CTO at Forte Design Systems and Andrea Kroll vice president of marketing and business development at JEDA Technologies. What follows are excerpts of that discussion.

LPD: As we go down the Moore’s Law road map, are there more variables to consider that affect power?
Buric: You can trade off area and performance for power three or four ways just by modulating the gateway. You can implement three different sets of libraries because you are concerned about leakage. But you have to contemplate all of that on a system level because you want to verify that it matches your spec.
Sanguinetti: There are new constraints that are being put on whoever is providing that input. If it’s an engineer writing RTL by hand, he’s got to do those. If it’s a synthesis tool providing RTL, it has to do the right thing. Ultimately, one of the biggest problems we’ve got is understanding what’s going to happen downstream.
Buric: Very often, when we talk about system-level design, we are talking about SoC-level design. More and more, system-level design will be partitioning between multiple SoCs. You will have a completely different set of problems with interfaces, which work at multiple gigahertz speeds. You have to find a way to model and verify. Today, ESL doesn’t do that.

LPD: Are you talking about board-level design?
Buric: Everything we’re doing is SoC-centric right now. We do not contemplate what happens outside the chip.
Kroll: Companies like VaST and Virtutech are working with Freescale and the big networking companies to look at those issues like Internet connections and other connectivity problems. While it’s not perfect and automated yet, there are known steps of how you get from one area to the next. To me, ESL is coping with the complexity of the systems at the moment. It’s not one person who can do this, either. So you need to work in a team and share resources. Then you have a flow with high-level synthesis and possibly more flows to incorporate IP.

LPD: The definition of what is ESL is changing. What will ESL be in two to three years.
Sanguinetti: ESL is just a convenient acronym for the next level above RTL. It’s just going to grow.
Buric: It is whatever specification the system needs.
Sanguinetti: You can apply that to RTL, as well. And you can do FPGA prototyping. That’s how people are doing full system simulation. It would be nice if they didn’t have to do that.
Kroll: To me, ESL mimics hardware and software timing at a system level, and then being able to break it down into the right flows. That’s compilers and operating systems on the software side, and on the hardware side it’s implementation from flow to silicon.
Ng: With so much of the leading edge being driven by the consumer and form factor, the ability to do this design exploration and try out different types of architectures and splits between hardware and software, get to the optimal implementation and minimize the risk of issues downstream is really going to be the boundary. One of the biggest gripes in cell phones and laptops is battery life. Battery technology is only progressing at a limited rate. A netbook that last nine hours is going to get more attention than one that lasts two hours. It’s not so far off you’ll see a quad core in a smart device you’re carrying around all day. The need for power efficiency will go all the way back to the system design.

LPD: ESL used to be all about the best possible design. Is it changing to just getting the chip out the door?
Ng: I think so.
Sanguinetti: With our first customers, they didn’t do design exploration. That was okay for that time. As these SoCs are getting more complex and algorithms are getting more complex, this design exploration has gotten to the point where people are paying more attention to it. If you can get a chip to the point where the first tool in the chain will swallow it, then everything down the chain will work.
Kroll: ESL started out as architectural exploration. The realistic view is, ‘Well I have my product and I want to add more functionality.’ When you want to get a product out, you add a little bit. A lot of tools were not ready to do that. You assume you start from scratch. At the end of the day, the shift will go to getting the chip out. But as you understand more of the process and the tools can handle it, there will be more exploration. That’s probably five or six years out, though.
Buric: The last three to four years, what I’ve seen is companies overdesigning functionality and then cutting it out. They reserve additional function and give it to customers who need it.
Ng: We’ve seen that, as well. It’s on-the-fly additional capabilities. If you can’t get it working on time, de-code it out. It’s fairly common.
Sanginetti: We had a customer where the first spec had 10 processors. If they had gone forward with this spec, it never would have been successful. It was programmable, but it never would have been able to compete on power consumption and area with a hard-coded solution. We could show them with ESL that you could cut it back to four processors.

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