Experts At The Table: Mobile Design Challenges

By Ed Sperling
Low-Power Engineering sat down to discuss the increasing challenges of designing for mobile devices with Qi Wang, technical marketing group director at Cadence; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Bernard Murphy, CTO of Atrenta; and Dave Reed, senior director of marketing at SpringSoft. What follows are excerpts of that conversation.

LPE: How real is wide I/O?
Wang: If you have unlimited resources and no restriction on packaging costs, even on the chip you can have wide I/O. You always want I/O as wide as possible. With 2.5D and 3D that will be the driving force. All the IDMs will keep developing the fancy stuff like FinFETs. Traditionally you go through the gate using source and drain, and the reason you have so much leakage is that your gate is so far from silicon that you control the other side. If you turn it around and put controls on the top and bottom of the silicon, the leakage is almost zero.
Reed: Other things that mobile drives is super-integration. Almost every chip we see has analog on the same chip as digital. That’s a noisy environment. You have to raise the voltages. But now you’re on a more advanced process than in the past, and some functions are moving into digital that used to be in analog. It’s done for power and availability. That’s a new architectural tradeoff that people have to make. Do they move it to digital or leave it in analog? Plus, people need automation there.
Murphy: Is the same thing happening with RF?
Reed: RF is coming onto the chip as well, but there are not the same tradeoffs as there are with other analog portions.
Murphy: I remember discussions about mono-chips where the whole smart phone including RF is on the same SoC.
Reed: I remember those discusssions, too. We had to give up gallium arsenide for a long time for RF.
Wang: One side of mobile is cost and low power. The other side is the signal. Anything that communicates with the outside world is analog. So every SoC is a mixed-signal chip by definition. We saw the same trend of moving things to digital. One reason is power. The other is when they define IP, they want to make it more configurable. They want to program those analog features. But analog is hard to migrate to the next node. If you move to digital it’s easier to migrate. So if you combine mixed signal and low power, that’s one of the big shifts in the market.

LPE: Do the tools exist for that?
Reed: I haven’t seen many. Are there any at the architectural level?
Wang: No. Right now we do it with a service team. It’s all manual.
Murphy: We’re seeing a lot more errors coming up around the mixed signal integration, too. And they’re subtle errors. When you put mixed signal together with power management you have things like level shifters and you find things aren’t quite characterized where you expected them to be or in the range you characterized them in. Something switches and the other side doesn’t switch. That’s a big challenge.
Chin: That whole verification area is tough. You can view the low power verification world today as a move in the direction of mixed-signal verification.
Wang: It originated from our old technology. We repositioned ourselves. Our previous methodology to speed up the design flow was analog and digital. The analog dealt with analog and the digital dealt with digital. Analog is a black box. You don’t even ask what is inside. The other side is the same. But that has to be changed. As ICs become more complicated, you can’t treat them as a black box anymore. It all has to be modeled and verified. The other side of this is that to move from analog to digital you have to do co-design. We are nowhere close to mature on that, but analog and digital engineers are working together because low power has to be considered as a whole.

LPE: But most of the engineers working in these fields live in silos. What’s going to change that?
Wang: On one side, the EDA vendors have to educate them in this methodology. There are a handful of very advanced companies in the world, but they don’t share their knowledge. To move the whole industry forward the EDA companies need to step forward. But we are starting to see more solutions architects to drive low power and mixed signal. I just came back from Taiwan and was promoting mixed signal models. The customer said they didn’t think that was a problem at the early stage. They would test a chip, find out what works, and go back and design another one. The customer acknowledged they will need to change in three to five years, but things will slowly happen.
Murphy: It’s not just Taiwanese companies. U.S. wireless companies accept they will have to do multiple spins because they cannot fix the mixed signal problems on the very first silicon. They’re going to put in enough redundancy to test it, and then they’ll fix it in the next one.
Chin: That’s really the testament to the need for tools in this space. When the customers are saying it’s going to fail, something is needed.

LPE: Let’s go back to the tradeoffs between Wide I/O and smaller I/Os. Do companies really understand this?
Chin: It’s the same problem we’ve been seeing on chip for a long time. It’s also related to this idea of dynamic power. What we’ve done for 20 years is optimize logic for performance, which means we care about the critical path. The way we optimize the critical path through synthesis is by trading off slack on other paths. You get a wave of transitions running through the chip. It’s an interesting tradeoff, because from the standpoint of power there’s nothing worse you can do. When you think about it from the standpoint of energy efficiency for computing a function, you have logic computing that function with a minimum of transitions and that’s it. Through this process of optimization we’ve folded everything onto itself. It’s re-use and resource sharing at a high level, but if we’re not reclaiming energy then design methodologies will have to change completely. Some smart EDA person will invent a new tool that allows you to push forward with this old idea of not folding your logic or sharing pieces so you can achieve the lowest possible power. That’s exactly where these tradeoffs happen. 3D IC is one example for the packaging level. Within the chip, within the synthesis domain, the system-level domain, the whole idea of architectural assembly of IP and blocks, this plays itself out many ways. It’s an important concept with regard to dynamic power. It’s fundamental. It’s the multiplexor problem.
Reed: If you look at the way the CPU guys have gone, they’re already down that path. They’ve stopped frequency scaling. You have separate cores. You can shut these things down or run them slower. They’re using the silicon to buy better power.
Chin: But you have more stuff sitting there that’s inactive.
Wang: If you look back 30 years, the most expensive thing was silicon area. At that time you had to do resource sharing. You went from parallel to serial. Now we are taking mixed signal to parallel.
Chin: And massively parallel is just one function computed optimally for everything that comes out of a chip. Maybe you expand that to 3D IC where each one of those has it’s own I/O. It’s interesting to think about how the methodologies and flows will have to change as we move in that direction.
Murphy: Architecturally, people are doing that on SoCs. Instead of one big DSP or CPU, they’re moving more and more of this stuff apart. There are multiple CPUs. The bus structure is split into many levels of hierarchy so you can shut big chunks of it down.

LPE: How low can we drop the voltage? Is it just 0.7 volts or 0.8 volts?
Wang: It can go much lower than that.
Murphy: I’ve heard 0.1 volts.
Wang: It also depends on the size we go to. You can get down to 0.3 or 0.2 volts without any problems. If you keep the aspect ratio of the depth and the height of a FinFET then you can guarantee the performance, but you do have other physical effects. Nothing is free. But the voltage can go much lower than what the textbooks say.
Reed: The rate of voltage scaling has been slowing. Leakage was the consideration that has been slowing the rate of scaling, though.
Wang: Absolutely, because if you look at a traditional 2D device it’s harder to control the channel so the leakage is a problem. But we can continue dropping it for a long time to come.