Experts At The Table: Retrofitting Older Process Nodes

By Ed Sperling
Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in front of a live audience at the Global Technology Conference in Santa Clara, Calif.

LPE: Is it harder to sell EDA tools for older nodes?
Heinlein: On one hand, the EDA requirements of the industry are evolving quickly. There’s one challenge where people have older tools, and you have to do new IP based on older flows. And then you have people wanting to use new tools on older nodes. They may want to use things like CPF. So we have this schizophrenia and we have to support that.
Kapoor: EDA is about tools, IP and services, and the reason the design components start to come in is that when you get to new nodes or existing nodes, you have to go broader than just tooling.
Sherwani: If you are developing tools for 14nm you are dealing with FinFETs and a lot of physical effects. But at 0.18 (microns) the issue is how to make one or two designers very efficient. We need to hire operations business people who have nothing to do with design in order to change that. EDA companies are very much focused on physics and getting to 20nm and 14nm. They still don’t have the mindset toward finishing a 0.18 design in one day. Is it possible to put together a flow that can be done by only one guy? In addition, many designs are derivative designs. Companies may want to add DDR3 to an existing design. The headcount and mindset required is very different.
Kapoor: We were joking before this panel that somewhere between the 34th and 43rd minute if I’m on a panel with Naveed he’s going to ask for free tools. With all due respect, that’s not a business we’re in. But in our core EDA business, we spend a lot of time on engineering efficiency. You will see a set of capabilities from Cadence that will address that. But if you can get an engineer to do a 180nm in a day, we should spin off a business.
Sherwani: The tools are focused on efficiency, but not on whether you can do designs in a day. If you can do a design in a day, you still have to verify that.
Ng: The point Naveed is raising is a cost issue. Whether it’s at the leading edge or older nodes, cost is in the purview of whether it even makes sense to do the design. Years ago when I was at Cadence we had a seven-day design goal. EDA hasn’t always looked at driving cost and efficiency.
Kapoor: First and foremost, EDA is about density and automation. The second part is that you have to figure out how the economics of the whole industry work. If at 40nm we spend $600 million putting together technology, to have anyone design at that node you need sufficient volume to get an acceptable return. And at 28nm it’s $1 billion and at 20nm $1.5 billion. You have to recognize that everyone can’t have an apps processor. That’s not going to happen. Just like there are limits to technology, there are limits to economics. If that’s what it will take us to put into it as part of the broader industry, that’s what we’re going to have to bear.
Ng: Do you think EDA has been driven to the same level of efficiency as other parts of the supply chain?
Kapoor: That’s not a fair question and here’s why: The way the business model for the tools piece works is different than for the semiconductor manufacturing. In the long term, if we bring on additional services will we look to be more in line with other parts of the supply chain, including Naveed’s business? Absolutely.

LPE: If power was not an issue at 180nm in the past, why is it such a big issue now?
Heinlein: Because the bar always moves. People are looking at applications that require low power much more than before. We also need to have power management ICs alongside other chips. And there’s a question of using the right hammer to solve a problem. The bar is different than it used to be.
Lukanc: The mix of things you put in a chip is different. There are mixed signal and power management. You can get a 40-volt PCB process at 0.25 microns. Now 30-volt processes are available at 0.13. You can mix things together and keep mask costs relatively low. Time to market is shorter, investment is lower and it requires fewer people.

LPE: What does the ecosystem look like with more foundries at older nodes?
Sherwani: These are not like TSMC or GlobalFoundries. They have their own IP houses or in-house IP.
Heinlein: That’s correct. These are companies that are very comfortable in their niche markets. That said, we are starting to witness sea changes in areas such as embedded microcontrollers, driven by the so-called Internet of things. That’s going to drive people to put microcontrollers and processors in places where they’ve never been before. Enabling modern software development and EDA development allows you to do more.
Kapoor: If you’re talking about a transducer or something like that, you’ll have to integrate the increasing analog and mixed signal capability with the digital capability. A mature node makes perfect sense. What you have to learn is what you need from the EDA side all the way to the manufacturing side.