Experts At The Table: What’s Next?

First of three parts: Difficulties are myriad at 28nm and 22nm, but at least power is part of the discussion with area, performance and manufacturability.

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Low-Power Design sat down with Leon Stok, EDA director for IBM’s System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys’ Implementaton Group; Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta. What follows are excerpts of that conversation.

LPD: What are we facing at 28nm and 22nm that we didn’t have to deal with before?
Murphy: If you’re not Intel or IBM, this may not be a problem right now.
Domic: 28nm and 32nm are just starting right now. People are just completing libraries, qualifying tools, and trying to figure out what else needs to be done to support today’s technology. There are two very different issues. One is what we need to do from an EDA perspective to support technology. The second is what are we going to design and what are the programs we will use. These chips are going to be very large and expensive.

LPD: Is it the same problem at 22nm?
Domic: Going to 22nm is even harder. What do you do for OPC (optical proximity correction) because of double patterning. That’s a technology issue. The second issue there is whether we will be able to afford a 22nm chip with 500 million or more cells.
Subramaniam: From an engineering point of view, there are two aspects, as well. One is design engineering, and the other is manufacturing. What is required for design? At eSilicon, we’re beginning to do things at 40nm now. We’re a mainstream designer and we expect that by the time 28nm and 22nm are mainstream they’re going to look similar to 40nm and the tools will be developed and tested by that point.

LPD: Do you really think that’s going to happen?
Subramaniam: That’s my expectation. I don’t know what the reality will be. But every generation of technology has necessitated new things. Leakage power is one issue. We had to address that. There are on-chip variation issues that need to be addressed. Timing and multiple corners need to be addressed. These are the kinds of evolutionary steps that needed to be taken from 0.13 microns. One of the things we’ve been hearing about 28nm and 22nm is stricter design rules in terms of how we design certain silicates and single-dimension versus multiple dimension design.
Stok: When we look at 32/28 we think we know how to do it. There are not going to be any drastic changes with wire tunes or basic design principles. We’ll have to deal with some binary effects and will need a little bit better tools. We don’t anticipate a huge problem getting through 32/28nm, but 22nm is a big step forward again. The problem is that lithography is not progressing.

LPD: Is that because EUV isn’t ready?
Stok: That’s part of it. We cannot improve the aperture or any of the physical metrics of the litho system in the 20nm generation. It all needs to come from computational lithography. OPC was an early version of this. Computational traits need to be placed on the shapes to ensure that they more or less print accurately. People are going to fill in those pieces in different ways. The key to this generation is how we’re going to limit the freedom of the designer while still having a very economical and feasible next design point. The ability to put everything on a design that is not explicitly forbidden by the design rules is, unfortunately, over.

LPD: So where is the differentiation going forward?
Murphy: Let me try an indirect pass at that question. An interesting question here is how you tie the revenue you’re going to make on a design to a significantly higher NRE for that design. I’m already hearing from a number of companies that they have to make a minimum $100 million on a chip to justify the NRE. There was a wonderful glory period where cell phone chips could do as much as $500 million, but now the lower end is creeping up. You’ll need more and more ways to justify building these chips, and that might have consequences for the design approach. We’re seeing a lot fewer pieces of silicon being built. Design starts are going down and complexity is going up, and that’s going to accelerate. You’re going to have find ways for a piece of silicon, maybe through software, to hit more sockets given these NREs.
Domic: That is the economic picture. But from a technology standpoint, one of the big successes of the EDA industry is that we have managed to keep up with a cell design methodology. That has managed to go through from 0.35 microns to 40nm. In general, we did well with this. I believe that with 20nm and 32nm, some of the restrictions that Leon mentioned are actually positives for the EDA industry. If you want to be stricter on what is vertical and what is horizontal, the task of the router becomes easier. Certain standards make the automation easier at 28nm. At 20/22nm, other questions begin to appear.
Stok: The economic point is important. Up until now, I had given up the hope that we could rein in designers. They would always come up with arguments why they wanted the last pico-second or pico-joule or whatever piece of power. Companies now need to figure out how to do things on budget, and that means doing things differently. That means putting a cost on any variations or anything outside the box. The tricky part will be putting a model back together that prices these extensions appropriately. When I buy EDA tools these days, I assume they can do everything I throw at it. That’s a given. I’m not paying a dime extra to route some exotic rule for me. I assume it’s going to work for my 32nm and my 20nm rules. I expect the same from my library provider. So we can get to the point where the base offering is ‘This,’ and if you want more you pay extra. If I can re-use an existing methodology and re-use IP blocks—even if they use 10% more power—then suddenly NRE can be cut in half. But can we price that into the ecosystem?

LPD: What happens if you don’t do that? It may be a case of natural selection because of both development time and cost.
Domic: But these things take time to operate. We are used to fairly exotic requests.
Subramaniam: The problem is that designers are used to getting everything they want today without paying an extra dime. They will continue to push for it. It will be very difficult to tell a designer you cannot use that. And the companies have been feeding them with solutions without charging them extra for that. For the IC industry in general there has been a problem getting value because historically a lot of people have been giving everything away. It is a challenge.
Domic: The direct connection between what an enhancement costs for an EDA tool vs. the benefit on a chip is very difficult to draw.
Stok: If you have a block that runs at 1.5GHz and you need to get it to 1.3GHz to get a little bit of power back, are you going to redesign it?

LPD: Will we be able to find a different solution than restrictive design for saving costs?
Domic: What is printable in a predictable way is much higher with restrictive design rules. If you take a look at the amount of processing that gets done to create a mask now it’s an extreme amount of computation already. In the future you won’t have to say, ‘No,’ to the designers. The foundry is going to do that for you when they say it cannot be printed. Period. End of discussion.
Subramaniam: Manufacturing has always been the savior in the silicon industry. They’ve always found the solution to every problem. My hope is they will continue to find ways to solve problems.
Domic: That’s true, but certain things have disappeared. Ten years ago we talked about routing at 45 degrees. Technically it was feasible, but economically it was unfeasible. We could build supersonic planes 30 years ago and we can build them today, but we don’t. It’s not because the technology can’t succeed. The cost is too high. Manufacturing may sort out some of these issues, but there is a point where the extra cost of doing it is not worth it. Certain types of restrictions, like single directions of some layers, make life easier for EDA instead of making it more complicated. The cost to designers is less and they can differentiate with something else.