Extraction, Power And Final Silicon

By Ann Steffora Mutschler
As semiconductor technology scales down, manufacturing effects are coming front and center, putting constant pressure on design teams to make sure that silicon can be modeled through the extraction process while performing analysis accurately.

Extraction technology is one of the basic components needed to gain an accurate measurement of power, timing and signal integrity.

“Device characteristics are changing from what they used to be,” said Sudhakar Jilla, product manager for place and route at Mentor Graphics. “In the past a simple resistance and capacitance calculation of a given wire segment used to be sufficient to do any timing, power, signal integrity analysis. What we have seen, especially going from 65 into 45 and now 28 and even 20, is that the device has big fat short wires vs. thin, long wires. As a result, traditional programming methods are no longer sufficient to capture the electrical behavior of your wires.”

That means more corners to consider in each design, whether it’s power analysis, timing analysis or signal integrity analysis. And at each node, there are a lot more corners because there are more components, more interactions, and much more complexity. That complexity and the changes within a design aren’t necessarily taken into account in the overall tool flows, requiring the addition of device and parasitic extraction tools.

“The problems are getting a lot more complex in terms of extracted devices and the parasitics all at the same time, and making sure they are properly hooked up through the extraction,” explained Harish Kriplani, R&D group director in charge of power analysis and IR drop analysis at Cadence. “There are a lot of manufacturing effects that need to be taken into account, and that’s where the complexity is coming from in the flow.”

Data sizes exploding
The focus on manufacturing effects, the sizes of designs, and the drive for better extraction accuracy also has led to an explosion in data from extraction. Design teams are challenged to manage the data while still analyzing it in a reasonable amount of time. To handle the billion-plus pairs of elements in some of today’s cutting-edge chips, EDA tool providers have invested in parasitic reduction while also increasing the capacity and performance of solvers and equipping tools to leverage threading and parallel processing to compensate for long runtimes.

To address the need for more accurate modeling, EDA tool developers take into account issues such as corner capacitance, fringe capacitance and other electrical effects that weren’t critical at older process nodes. However, because of the proximity effects at smaller geometries, corner and fringe capacitance is examined more closely now.

In addition, designers are running into huge brick walls when they don’t include the package in their modeling of the whole system—inductance, package and the capacitance on the chip. This creates a whole different kind of power analysis environment that you have to consider. Otherwise your chip will work fine on the tester, but when you plug it into the package it may not work, said John Kane, senior product marketing manager for timing and power tools at Cadence.

From an implementation and sign-off perspective, even when it comes to just the pure layout of the wires and the effects, the extraction model has become a lot more complex. “You need to look at not only the length and width of the wires—you need to look at the neighbors, the top and bottom, the layers below and above, to capture the complete effect of what you are talking about,” said Mentor’s Jilla. “Especially from an implementation perspective every optimization that the engine tries needs to look at the timing and power and signal integrity affects. And this has ripple effects throughout the flow because all the pieces are tied together. Most of the power analysis in any implementation system traditionally used to look at power and SI only after the timing was met. Now as we are going down the technology curve what we are seeing is that all of these analysis must be concurrent.”

Going forward to 20nm and 14nm, technologies such as double patterning and triple patterning enter the picture, complicating matters further.

“The other axis of this whole thing is 3D. Now you’re basically adding one or two more levels of complexity in this whole modeling and what things need to be considered during extraction. If we thought it was hard before, it’s going to get even more challenging going to 20nm and 14nm—especially with respect to power. The way our extractor works depends on where you are in the flow. The extraction accuracy and runtime tradeoffs change. That is needed because, for example, during global routing or in the floor-planning phase you just need an estimate of what the Rs and Cs might be. When you go toward the end of the flow and you have the actual detailed routes in place you can extract more accurate numbers. It’s like a dial. In the beginning you have accurate enough but very fast. Toward the end, after the implication flow when you have that detail post route, you go for the full accuracy.”

Power budgeting needed
While extraction can provide extremely valuable information to the design team, there is also the issue that next generation chip architectures are no longer constrained by silicon area or library speed. What becomes critical is the power they can afford to consume and the allowed heat dissipation. Chips must meet maximum power specification limits to control the widening imbalance between what the system will consume versus what it can consume to be competitive.

“Below 28-nm, a lot of customers are requesting that we narrow the band for power budgeting,” said Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions. “Budgeting, very simply put, is different modes of operation on a cell phone, for instance. The power consumption varies dramatically because different stimulus is applied during different applications. To be able to reflect that in the power grid design is a very difficult challenge. How do you predict that at the RT level? And how do you select the high power consuming vectors from the millions of cycles you have?”

There is a need to bring physical effects up in the design flow to predict what happens to the RTL power downstream—after synthesis, place and route, and clock-tree synthesis. A big technical challenge is making sure that the range of power numbers predicted early in the design are maintained throughout the design process—and also that the numbers collected early enough in the cycle actually work in final silicon.

Beyond the standard issues of timing closure with accurate and fast grid extraction, the RC will surely play an important role in other part of the overall power, noise and EM analyses. The capacitance (“C”) modeling of wires and clock structures can be a key element in modeling the impact of these at an early RTL power planning stage and can be a part of a power budgeting flow. At the same time, the accuracy of the resistance (“R”) part of extraction is expected to play a role in electro-migration analysis of power grid as well as for signal-EM, and will be critical as the industry embraces 3D structures.