Extreme Ancestry: Silicon Edition

The ability to trace the genealogy of all the components in an electronic device has been getting more complex for decades. For many industries — automotive, defense, medical and others — the need to locate the source of a problem in near real-time is paramount to gauging the extent of that problem. The extreme case is when the issue occurs with a product that already has been distributed and used in the field. Complicating matters is the fact that the current chip shortage is pushing chip designers to second- and third-tier suppliers for their inventory.

Tracking information is not easily done given the number of times material can change hands during the manufacturing life cycle. Designs can incorporate IP modules from Parties No. 1, No. 2, and No. 3 (figure 1). These designs are blended into a singular chip by the device’s Design House. This chip is then built at Front-end Foundries No. 1 or No. 2. The completed chip can be tested and partially assembled at OSAT A, B, or C. Finished assembly into a multi-chip module (MCM) or printed circuit board (PCB) can take place at Assembly House No. 1 or No. 2 (or happen at Customer A if they provide the IP for a design for a device that can be assembled by Finished Goods Maker No. 1) before it is finally sold by the Design House to the End User or Final Goods Manufacturer A, B, C, D and more for insertion in their end product, after which it is again tested before being sold to the end customer.

This is a very simplified example of how complex a supply chain can be, but it is illustrative nonetheless.

Virtual v. physical traceability

At some point in the supply chain, units receive a physical marker that enables traceability as it progresses through the remaining chain of manufacturing agents. Prior to the application of a marker, reliance on a part’s origin is a function of accounting and accurate recordkeeping. Although this seems simple enough, it is complicated by the transition of “ownership” of the chip as it moves through the supply chain.

Tracing a chip’s origin includes its transformation through multiple physical form factors. These material changes frequently include moving from a lot/wafer/die physical structure to a singulated die on a piece of tape or reel to an assembled die in a package, or in a tray, or as an inserted chip in a multi-chip module or PCB — ultimately ending with the PCB being inserted into a larger form factor, such as an automobile or a computer server. Each time the physical form factor is updated, there is a chance to break traceability in the supply chain if incoming and outgoing product labels are not meticulously documented. This is exacerbated by a lack of standardized data formats and communication frameworks throughout the supply chain. All too often, there is a gap in a unit’s back mapping. Once this occurs, any chance to trace a problem to a source is jeopardized.

Fortunately, every day there are better tools and more comprehensive data structures helping reduce traceability errors.

Data relationships

The challenges of physical traceability pale in comparison to the challenges associated with applying data to the chip as it is moves through the manufacturing process. Associating a wafer-level value to the chips residing on a wafer during manufacturing is just one aspect of this problem. Associating all the test results for a PCB to all the die on a PCB and then mapping those values back to the wafers those die originate from hints at the scope of the problem. This is truly a “N” to “N” data array relationship space. New analytic tools, especially those in the machine-learning arena, can help elucidate these data relationships.

Analytical availability of data

Silicon chips are finding their way into more quality-centric applications. To perform analytics properly, especially from a diagnostic engineering/quality validation perspective, having data on the actual device is paramount. The odds of having complete data on any one device, let alone all the devices in a MCM or PCB finished product, are extremely low. The ability to identify any, let alone all, parameters associated with the construction or testing of a specific chip, module or board is next to impossible.

Today, factories are set up to monitor processes with the goal of maintaining operational control. In a factory sampling 2% of all materials processed, collecting 20 individual points for an individual wafer results in collecting 40 points per every 100 wafers processed. If these wafers have 500 die per wafer (DPW), the chances there is a location match between die and the in-line metrology sampling point are 0.0008%, or one in every 1,250 die processed. Essentially less than one-tenth of one percent of material has the needed metrology data to perform direct analytics. As sampling strategies are challenged due to cost reductions, the chances that an abnormal event is discovered at the end-of-line test increases. All non-matched die will have to go through an assumption-based data expansion to create a necessary data association. These expansions are frequently executed without any consideration of error bars.

Given the current chip shortage, factories might be forced into quicker turnarounds of unit deliveries, while still needing to maintain quality levels. With tight delivery timelines, the traceability of data to the die level is even more critical, as quick identification is needed to either do a recall or an infield, over-the-air update of software for affected parts. Some smart modules in the field send real-time monitoring feedback to the manufacturers, whereby this data is fed back to their factory systems for optimization on certain tools using traceability/genealogy history.

Gone are the days when a company would design a chip, manufacture a chip, assemble and place that chip on a board, and sell that board to an end user. Today, the reality of longer and more complex supply chains must be dealt with. These longer supply chains must also include greater levels of analytics that end up being driven by higher quality and die-origin requirements to meet specific market segments that are expanding tremendously in the semiconductor space.