Facing Up To Reality

Welcome to the world of power awareness. Engineers are well aware that just as timing and area were previously separate considerations in the chip design process, power is also now a top-level consideration.

In this blog, we will examine issues related not only to low-power in chip design, but the wide-reaching topic of power-aware design overall. Engineers today must consider the impacts of power on many levels and in various realms. This can certainly include low power considerations for handheld devices, but also in terms of how a particular chip may require additional cooling in a data center should it be installed in a rack mounted 3U blade, or even making sure the tester can understand the design intent when the design includes multiple power islands and voltage domains.

As I wrote recently in the article, “Combining Power And Synthesis,” each passing design node has made power management a critical design priority – even in the synthesis step in the design flow. Synthesis has always been an integral part of the design process, particularly at the RTL level. But as chip design has become more complicated, the need to raise the process up a level of abstraction into high-level synthesis also has started gaining traction. What’s new is the inclusion of power management in both steps.

“Just like closing on timing or closing on area, closing on power is a responsibility of the synthesis tool including a high-level synthesis tool,” said Thomas Bollaert, product marketing manager for Catapult C at Mentor Graphics Corp. in the article.

Further, high-level synthesis can now be power-aware as well. While there are certain widely-adopted low-power techniques – such as clock gating, which is critical to understanding how much dynamic power can be saved – that designers typically use and implement when doing manual RTL coding, these can take a lot of time to do by hand and can be error-prone. High-level synthesis has the potential of making the analysis and the transformation automatically on behalf of the designer thereby generating much more power-efficient designs.

As is the nature of a blog, we welcome and encourage your comments, questions and feedback. What are your biggest concerns with power-aware design? We look forward to your input.

~Ann Steffora Mutschler