The Low Power-System Level Connection

I don’t know about you but I am fired up (in a good way) with everything surrounding low power and design at the system level. We are at a point where the challenges are pretty well understood, we can see the way forward in many areas, but what needs to happen next is the evolution of technology that will compel users to adopt the new techniques, which may have yet to be created. Engineeri... » read more

Giant Steps—Backward

With DAC headlining next week, power is sure to take center stage given its prominence as a key pain point for design engineers that are always on the lookout for a new technique to ease their power management burdens. In many low-power designs, asynchronous technology may be just the thing. One of the biggest disadvantages of the clockless CPU is that most design tools assume a clocked CPU ... » read more

Facing Up To Reality

Welcome to the world of power awareness. Engineers are well aware that just as timing and area were previously separate considerations in the chip design process, power is also now a top-level consideration. In this blog, we will examine issues related not only to low-power in chip design, but the wide-reaching topic of power-aware design overall. Engineers today must consider the impacts of... » read more