The Next Big Leap: Energy Optimization

The relationship between power and energy is technically simple, but its implication on the EDA flow is enormous. There are no tools or flows today that allow you to analyze, implement, and optimize a design for energy consumption, and getting to that point will require a paradigm shift within the semiconductor industry. The industry talks a lot about power, and power may have become a more ... » read more

Dealing With Sub-Threshold Variation

Chipmakers are pushing into sub-threshold operation in an effort to prolong battery life and reduce energy costs, adding a whole new set of challenges for design teams. While process and environmental variation long have been concerns for advanced silicon process nodes, most designs operate in the standard “super-threshold” regime. Sub-threshold designs, in contrast, have unique variatio... » read more

Searching For Power Bugs

How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

Exhaustive Verification of Reset Domain Crossings

It is difficult to imagine an aspect of semiconductor development more fundamental than reset. The ability to initialize the entire hardware design and clean all software running through a system-on-chip (SoC) is essential. Stating with a known state avoids propagation of signals with unknown values. Despite the best efforts at verification, lingering corner case bugs may put a system into a st... » read more

The Low Power-System Level Connection

I don’t know about you but I am fired up (in a good way) with everything surrounding low power and design at the system level. We are at a point where the challenges are pretty well understood, we can see the way forward in many areas, but what needs to happen next is the evolution of technology that will compel users to adopt the new techniques, which may have yet to be created. Engineeri... » read more

Giant Steps—Backward

With DAC headlining next week, power is sure to take center stage given its prominence as a key pain point for design engineers that are always on the lookout for a new technique to ease their power management burdens. In many low-power designs, asynchronous technology may be just the thing. One of the biggest disadvantages of the clockless CPU is that most design tools assume a clocked CPU ... » read more

Facing Up To Reality

Welcome to the world of power awareness. Engineers are well aware that just as timing and area were previously separate considerations in the chip design process, power is also now a top-level consideration. In this blog, we will examine issues related not only to low-power in chip design, but the wide-reaching topic of power-aware design overall. Engineers today must consider the impacts of... » read more