Help, 3D-IC Is Stuck In A Country Song

Every time I focus on three-dimensional (3D) integrated circuit (IC) design, I start hearing the Luke Bryan song “Rain Makes Corn, Corn Makes Whiskey.” Not because I need a strong drink to work with 3D-IC designs, but because there is a similar, although slightly more complicated, series of cause and effect issues that impact 3D-ICs. Pushing electrons through very thin metal wires and switching devices very fast creates heat. Heat causes expansion, but different materials expand at different rates. These expansion effects combine with the stacking of dies, interposers, through-silicon vias (TSVs), bumps, substrates, ball grid arrays (BGAs) and other components to create non-uniform mechanical stresses. Then that heat and those stresses impact how we move electrons through wires and how devices behave, and we’re back to the beginning! How do we get this interdependent web of effects all under control?

At first glance, the solution might seem relatively easy: First, to understand the impact of how we’re pushing those electrons through our design, we run an electromigration (EM) and voltage (IR) drop analysis. From those results, we can generate a power map to feed into thermal analysis. Temperature maps from thermal analysis can then be passed to mechanical stress analysis, along with thermal impacts from both the die and assembly manufacturing stages. Then we feed the thermal and stress impacts back in to update the EMIR analysis. Easy-peasy, right? Not so fast.

To get EMIR results for a 3D-IC, we need to know the power grid of the design. But there are dozens of different possible ways to combine multiple designs into a single assembly, and within each assembly, there are multiple choices of chiplet placements. These placements are no longer constrained to just two dimensions, but now can also be stacked vertically. Given that these multi-physics issues are going to impact electrical performance and behavior, determining which assembly approach to use and then which chiplets go where to generate an optimal assembly is a big challenge. The ultimate solution would involve place and route (P&R)-like tools that can optimize across 3D placements, including optimizing across all the multi-physics impacts. Unfortunately, despite all the hype, such a solution is still quite far off.

A short-term alternative is to start with several different assembly types, based on a set of initial goals for the total 3D footprint. 2.5D approaches, like fan-out wafer-level packing (FOWLP), silicon interposer, or embedded interposer in substrate approaches, will be a bit easier due to their having more constraints, whereas a true small outline integrated circuit (SoIC) style of design, with so many options, can require more effort. Multiple implementations of each assembly type would further help to identify “best” specific placements.

Similarly, working from known good die can also help through levels of pre-characterizations. Alternatively, even as dies or other components are incomplete, obvious thermal and mechanical stress issues can still be identified, based on best guesses for the material make-up of each component, with further iterations as the design is refined. Of course, this implies use of a 3D planning tool, such as the Xpedition Substrate Integrator tool from Siemens EDA, to quickly build out the different floorplans.

As an example, formats like the electronics cooling extensible markup language (ECXML) can capture thermal impacts for an individual die. When the die is placed in context within a larger assembly, it’s possible to re-use that data, adding the additional impacts. As we advance toward an automated approach, these multi-physics impacts (in theory) could be captured per chiplet, or at least for highly sensitive intellectual property (IP) blocks of a given chiplet, and combined with the parasitics to feed forward into something similar to today’s liberty (.lib) timing model files. Unfortunately, unlike the ECXML format for thermal, there is currently no such similar format to capture mechanical stresses, although there are multiple efforts moving in that direction.

It’s obvious that multi-physics can have a real impact on 3D-IC performance and behavior, meaning these impacts can’t be ignored. While all the major electronic design automation (EDA) companies and 3D-IC manufacturers are heavily engaged in solving this issue, there is still quite a bit of work ahead. True 3D design still requires significant manual analysis and review, and as such, presents a market risk. At present, it is still largely relegated to the very largest IC design companies that can afford the people and time to do this work until automated solutions become available. In the interim, 2.5D with known good die offers the lowest risk for successful package designs.

For more information about 3D-IC design management, check out our technical paper, Successful 3D-IC design, verification, and analysis requires an integrated approach.