How one company achieved first-pass silicon for a mixed-signal design.
While there are many benefits to migrating to smaller process geometries, such as lower power and higher performance, the increased design complexity places an even higher burden on fast and efficient simulation technology. In addition, fast and accurate resistor/capacitor (RC) extraction is becoming increasingly important. Interconnect resistance is an increasing percentage of the total path resistance. From 40nm to 7nm, the relative wire resistance has risen more than six fold and the subsequent RC netlist can increase the simulation time by 20x, adding to the simulation burden. In this paper, learn how Silicon Creations uses the Analog FastSPICE Platform to meet these simulation demands in order to create first-pass silicon for their 7nm IP.
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