High-Speed Interfaces Dominate New Designs

What’s possible in an IC isn’t always possible on a PCB, but changes are under way.


By Pallab Chatterjee
Displays, inputs devices and storage interfaces have now moved up into the high-speed multi-gigabit per second data rates. These were formerly Mb/s technologies, but they have moved into the Gb/s format. Adding a high-speed interface on a system is not the same as on an IC. PCBs do not have the luxury of Moore’s Law to drive the technology, so bringing new high-speed parts in systems is not as straightforward as finding new IP vendors and a new fab.

New embedded systems for the mobile marketplace are split between two form factors—handsets (less than 5 inches) and tablets (6 to 11 inches). These devices feature interfaces and connectors for a number of new high-speed specifications, including Display Port (DP), HDMI, USB, and SATA. The older versions of these specifications, such as USB2 were in the sub-500MB/s data rate range. The new sweet spot appears to be around 5Ghz or 5Gbps. DP now can support multiple lanes (up to four), with the per-lane data rate of 5.4Gbps for a total of 21.6Gbps. HDMI V1.4 supports more than 5Gbps for 16-bit and 24-bit color, the new SuperSpeed USB 3.0 specification at 4.8Gbps and SATA III at 6.0Gbps. On non-mobile, but portable systems (laptops, notebooks and ultrabooks) there is a possibility that Thunderbolt (up to 10Gbps) also may achieve traction, provided the system design can be addressed.

As these data rates move up, standard chip issues such as signal integrity, noise, impedance variation, manufacturability, package and board inductance, and power move to the forefront. On ICs these issues have been addressed by a number of design tools, but mostly by device and process performance, which has moved the material properties to a higher level where these speeds are obtainable on a reliable basis. The materials used for boards, cabling and system design have not fundamentally changed or migrated. The properties of copper as the dominant interconnect are pretty much unchanged for large sizes (mils of width for a trace or larger than 32-gauge wire). For data rates about 2Gbps, the nominal design process is to address all the PCB traces as microstrip and tapped transmission line design rather than “just interconnect.”

For these interfaces to operate at high speeds they need very short drive distances when the signals come out from the platform SoCs. These chips, due to the limited power profiles for the I/Os vs the cores, typically can drive under two to three inches of impedance tuned trace on a typical design. For handsets, this is now just a matter of chip placement on the board with respect to the connectors, but it is problematic for tablets and larger devices. In those cases, it typically isn’t possible to cross the entire board length of the design at the intended speed without the need for additional re-drivers or buffers. These additional parts also draw and drive power, typically at the higher (3.3v or 5v) power supply levels. As a result, there are thermal and noise issues related to the placement of these devices.

These buffers and re-drivers also are needed to support external cables. Typical passive wire length with certified connectors are less than 1 meter (3 feet). These intervaces need to run in the 3M to 15M range for device-to-device hookup. For these long drive lengths, the systematic loading and waveform shaping by the use of active cables needs to be addressed in the design of the board. These active cables also derive their power from the connectors, so the path for the power has to be addressed in the design and layout of the PCB to bring secondary power to the connectors.

The power issue is an interesting aspect for these specs. In addition to the high-speed data rate, some of these provide very high power factors. For charging mode, the USB3.0 spec has to support up to 100W (20A at 5V) for peak power, and nominal device connection is 900mA. For standard low-voltage SoCs, these specs are challenging as they will require the I/Os for the device to exceed the power and thermal format of the package. These power issues require the systems architecture, power planning, connectors and board layout to address power and thermal aspects of these high speed connections to obtain full-speed access to the data.