How IoE Will Alter Supply Chains

Globalization is a double-edged sword. Without a doubt, it nourishes competition, offers a plethora of independent sources, and bounty of supplies from a global pool of vendors. That is the good side. The downside is that control becomes a management nightmare. Well-oiled, traditional supply chains systems will have to be redesigned to function across a variety of variables that can interrupt the chain at almost a moment’s notice. And supply chain security and complexity take on a new dimension.

The supply chain is generally thought of as a single entity, and with the traditional closed-loop model that has been an acceptable approach. However, going forward, that model will change.

Tomorrow’s supply chain will segment into two or more distinct and individual vectors. On the production side, today’s model is well understood and much of that will port nicely to the new model. However, the engineering side is going to change. It will emerge as a unique and critical element that will require its own understanding, especially with semiconductor components.

To dig into what will change, Semiconductor Engineering sat down with Jim Aralis, Microsemi’s CTO.

SE: What’s your vision for how this model will unfold?

Aralis: The semiconductor business is changing in some very fundamental ways. A lot of what used to be standard semiconductor products, even SoCs, are becoming IP for larger platforms of integration. The chips are becoming more complex, hence the cost of these chips will increase dramatically. That will condense the foundries to a small concentration. And, this will change the traditional model of a fabless semiconductor company. Building the design from scratch, assembling it, doing verification, test, and the rest of the process, and then feeding it off to a fab and packaging house and finally receiving the product, will change in some very fundamental ways.

SE: What’s the big shift here?

Aralis: The entity that controls the IP will be where the fabless semiconductor companies will flock to. Simply put, the semiconductor manufacturers will no longer be able to afford to build future 10 billion transistor circuits from scratch. So this segment will need to acquire the building blocks as components.

SE: So what does this mean for the engineering supply chain?

Aralis: If you look around, you’ll see companies like Intel, Broadcom, Synopsys, Cadence, even Microsemi, and many others are building IP libraries. Foundries like TSMC are acquiring IP at phenomenal rates. So there is this movement within the industry, almost like a race to acquire the best and biggest IP library. That raises an interesting issue. Going forward, will the CAD companies be the ones who will control the IP and choose the foundry? Or will the semiconductor companies control the strings and the CAD companies deliver IP to them, almost like a service? This is a somewhat of a confusing issue. Will it be fabless semiconductor companies that own the IP, or will it be CAD companies that will enable a different type of fabless semiconductor company that will get the majority of the IP from them? Or will the foundry be the one that has the ability to do system-level integration and buy IP from the semiconductor vendor? That future version of the supply chain has yet to produce a definitive model, and the landscape might be a bit bloody before the smoke clears and we know how it will shake out.

SE: What will be the role of the design engineer in this new ecosystem?

Aralis: In this new model, the interface will be at a very high level. It may be possible to take the design, and with the right IP, to synthesize it directly into silicon. The circuit design or digital design will be done by designing and integrating IP at a much different level. So typically, circuit designers and engineers will be building IP block circuits in much higher level configurations, at the system level rather than the component or circuit level that is the current methodology. So where this will end up in the semiconductor supply chain is that chips are going to become superchips, with much wider functionality – super ASSPs if you will. Such ASSPs will have wide applicability in tomorrow’s equipment such as switching boxes, routers, CPE equipment. Then there will be FPGAs that will add functionality to these ASSPs. So the supply chain for this scenario is going to be a bit different than we are used to. The proprietary stuff will go into FPGAs and ASICs, but the ASSP will be designed so that with minimal programming you can do the ASIC function, even if there is a small penalty in efficiency. So in general, the ASSP will be heavily augmented with software tools that will allow programming for whatever function is wanted.

SE: What does this mean for the engineers themselves?

Aralis: Another change in the engineering supply chain will be the shift from hardware engineering to software engineering. The designers are moving toward a better than two-to-one ratio of software to hardware engineers, even in the areas we traditionally define as hardware. That is an indication of the move to the new paradigm of fewer chips, with higher levels of functionality through software loads. And we are not that far away from this shift. It will likely happen in the next 5 to 10 years.

SE: Once all of this is in place, what do you see as the significant benefits to all the players, as well as the end user?

Aralis: The one area where this will have a significant impact will be the IoE. It will be enabled by the incredible processing power, and flexibility of that processing power. Everything will be talking to everything else. However, this is a relatively complex metric and begets the concern about how to manage the massive amount of data that will be going around – and how to control it. One approach is to implement local processing. That can be a challenge because to accomplish that requires low power thinking and the chips have to be low power in order to deploy them as ubiquitously as necessary. That becomes a component of the chip supply chain that will be addressed by the super chips discussed earlier. However, local processing is a must, not an option, simply because the main infrastructure will be overwhelmed if all the processing is sent to the cloud. So the thinking is to put that processing into local devices, from aggregation points of sensors to routers, switches and the like. But in the end, and I say this with a certain amount of trepidation, we have all of this potential processing power—unlimited processing power. And we really don’t know what to do with all of the processing power that a 7nm processor, built on the highly integrated system that was discussed earlier, is capable of.

SE: Where’s the fallout on that?

Aralis: We are going to have to develop super-efficient algorithms so the processor doesn’t sit around and twiddle its thumbs waiting for the algorithm to finish. The end result to the semiconductor supply chain, and to some degree mankind itself, will be providing much more interdisciplinary applications with a variety of chips. We will have the capability to process data so fast that it will be difficult to come up with applications that can take full advantage of this new generation of hardware. We will have to work very closely with multiple disciplines from the physics, chemical, medical, biology, even the social scientists, to understand how to process data using this massive computational power. To that end, the semiconductor supply chain goals will no longer be to build a faster switch, or shorten latency, or increase clock rates. Processors and other chips will, simply, now be a tool that will be used to solve problems and improve the understanding of mankind.

SE: How will packaging be affected?

Aralis: Packaging will become a significant design metric. It is important to realize the nature of packaging is changing. For the longest time, packaging was not even a concern. It is no longer going to be, ‘Just choose a package and put a chip in it.’ It means that you will need to architect the package to accommodate that billion-transistor chip with perhaps another analog chip and a multi-billion cell memory. It will be part of the strategic design. Therefore, packaging will become very important as the industry moves forward, and will shift from a production element to a design element. One size certainly won’t fit all.

SE: There is no doubt that this new supply chain will alter the very fabric of chip security. Tell my how you see that taking shape.

Aralis: Security for this brave new world is a tough cookie. Of late, we have seen some very good state-of-the-art solutions. One of the major concerns, because chips can be made just about anywhere, is re-marking. To thwart that we use tattooing. The chips are cataloged for speed, what kind of part it is, and several other critical performance and function elements, so there is no way to change the specs. There is also software authentication so that the function that is loaded, for example, has a specific valid ID or it will not work. There is also the use of physical unclonable function (PUF) technology that makes it virtually impossible to pull keys. Another edge-of-the-envelope security measure is to ID the mask. That is a process that making sure that the mask is the correct mask for the part and hasn’t been tampered with, even by the same mask shop. Combined, this technology is a very precise way to secure IP and something we are working hard to implement in several channels. Putting all of this together places several layers of protection on our ICs and can guarantee the parts are authentic.

SE: How far along are you?

Aralis: We believe we are one the edge of this but other semi manufacturers are also working on similar technology. Ultimately, that means that any counterfeit chip, no matter how exact it is to the original, won’t work. Overall, with these new capabilities and technologies, it will be more and more difficult for the attackers to compromise chips. And finally, there is some interest in revisiting some earlier security technologies that are finding applicability for future technology. One of them that I find particularly interesting is the use of security systems that are adaptive – systems that actually learn their local network and adapt to what is valid and what is not. The nice thing about this is that every network becomes different, so potential hackers will have to start from square one in each network. This is an example of an old technology that can be adapted to modern networks because it is particularly challenging to attackers. In the end, the semiconductor supply chain, from inception of the system, to delivery of the part is going to change dramatically in the next seven or so years. It will consolidate; it will be a more complex landscape but with fewer players. And it will be more of a key element than we have seen in the past.