Hypervisors For Managing Power

By Ed Sperling
Hypervisors are headed for a new role inside of multicore chips—managing the various power islands in addition to the cores.

A patent application filed by IBM, entitled “Method and system for hypervisor based power management,” shows the company’s intention to use hypervisors for everything from monitoring power consumption rates to scaling power for individual cores. http://www.faqs.org/patents/app/20080301473

In the well-documented history of hypervisors, this marks a major shift in direction. Hypervisors have been used primarily for running virtual machines on a single or multiple cores and for directing applications to take advantage of one or more cores. In effect, they have worked like rudimentary traffic cops, scheduling software functions for processors, memory, logic and buses.

Adding power into the mix changes the basic concept in two fundamental ways. First, it means the operating system becomes less important in a multicore system because critical decisions about what gets turned on and off, how much power is assigned to different processors or other parts of the chip, and what gets prioritized are made by the hypervisor layer rather than the operating system. And second, it means getting chips out the door will become immensely more complicated because just thinking about all the possible permutations for verifying these kinds of systems makes your brain hurt.

“A hypervisor for low power management certainly can work,” said Marc Bryan, product marketing manager for Mentor Graphics’ Codelink products. “This is an extension into the SoC world and configurable IP. Software developers want middleware capability to control the power demands with the SoC.”

He noted this works in both multicore and single core chips and becomes particularly useful in chips with multiple configurable power domains, such as an advanced ARM processor that can contain 14 of those domains. But it’s also like building complexity on complexity.

“This definitely opens up a new set of challenges in design and verification,” he said. “You’re adding complexity in the power domain. The challenge is verifying it. You have to make sure the hardware switches on and off and that the software is included. And with power management software, you have to make sure you can turn on and off the power domain and that the software works correctly with the hardware.”

This is no simple feat. In fact, to the best of anyone’s knowledge, it has never even been attempted.

From the beginning
The concept of a hypervisor has been around for decades. IBM introduced the first implementation back in the 1970s with its System/370 mainframes as a way of virtualizing applications running on the mainframes to make them more efficient.

Fast forward to 2005 and that same technology showed up in the eight-core Cell processor, which IBM created with Sony and Toshiba. Sony used seven of those cores for its Playstation3, plus a hypervisor to manage all the cores. It was the classic example of smaller, faster and cheaper compared to the complex multi-million dollar mainframes that were the size of multiple refrigerators.

Almost simultaneously, the same general concept began showing up to manage virtual machines in virtualization software created by companies like VMware and Citrix, which allow multiple operating systems to run on a single core or multiple cores. They also allowed multicore servers to be utilized at greater rates than the average 15% to 20% that many were being run at, costing both power to run the machines and power to cool the server racks.

Using hypervisors to manage the power itself, however, is new and shows the resilience of this concept of adding programmable controls for functions that typically have been handled by hardware.

“The hypervisor is a way to really start giving us control over power in SoCs,” said EDA consultant Gary Smith. “Put that together with an NoC and you really start moving toward an ESL view of power.”

Market realities
It still could take years before this concept shows up in power management of SoCs, however. While there is a compelling need to simplify power management on chips, this may not be the only approach or even the best approach.

Right now, many of these functions are assigned to the operating system. It’s possible that the operating system can start offering these kinds of capabilities rather than a hypervisor, or that a more robust hypervisor will be built into operating systems.

But hypervisors, at least in IBM’s view of the world, have a distinct advantage. In IBM’s model, the hypervisor runs between the metal and the operating system, almost like an enabling set of middleware. The result is that it can take advantage of whatever changes are made to the hardware and whatever hooks are added much more quickly than those changes can be added into the operating system, where backward compatibility of applications is vital. (See Figure 1)

Figure 1: IBM's hypervisor design

“One problem with doing power in the hypervisor is in the area of security,” said Barry Pangrie, solutions architect for low power design and verification at Mentor. “If you’re creating a medical device and you put more into the hypervisor, that means the hypervisor layer now has to be certified.”

The flip side is that the hooks in the hardware are going to be much more readily available to a hypervisor layer built for a specific purpose than an operating system. “When you’re talking about dynamic voltage frequency scaling, for example, those capabilities tend to run well ahead of what the software guys are using when they write their code. One way to deal with that is to make the OS smarter and use some of the statistics dynamically to help bring down the power levels.”

Another way is to develop new code that wedges between the hardware and the operating system, which is one of the models now being considered in the virtualization world. But when this gets to market and in what form is unknown. What’s interesting is there is a need and a method, and from here anything can happen.