SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems

Abstract "Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures. Near-bank PIM architectures place simple cores close to DRAM banks and can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwi... » read more

Multicore Debug Evolves To The System-Level

The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches. Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact, so many pro... » read more

The Benefits Of Using Embedded Sensing Fabrics In AI Devices

AI chips, regardless of the application, are not regular ASICs and tend to be very large, this essentially means that AI chips are reaching the reticle limits in-terms of their size. They are also usually dominated by an array of regular structures and this helps to mitigate yield issues by building in tolerance to defect density due to the sheer number of processor blocks. The reason behind... » read more

Embedded Multicore: Enablement Of Heterogeneous OSes And Mixed Criticality Systems

The implementation of multicore embedded systems is becoming increasingly common. The decision to realize a design using multiple processors may be influenced by a number of factors; broadly these are technical goals to attain, a time to market to achieve, and target design and production costs. Using multicore in a design requires a number of key decisions, which, as with most embedded systems... » read more

Pushing Performance: Analysis and Optimization of Multicore Communication with SLX

In theory, multicore programming should be simple: Tasks are placed on available cores and allocated a data buffer in the shared memory to communicate data between two tasks. However, the amount of communication resources in the latest multicore SoC is very limited. One cannot deal with all the data communications required by all the tasks without being able to understand communication conte... » read more

Finding And Avoiding Concurrency Bugs

Understanding the intended and unintended interactions between hardware and software components is changing as architectures become more heterogeneous and interconnect topologies get more complicated. This affects performance, power consumption and cost of the project. Lots of universities are researching this from a software perspective, while a small number are looking at the implications fro... » read more

Multicore Software Design For An LTE Base Station

This paper presents a typical base station design scenario, where decisions about HW/SW partitioning, the number of processing elements, and operational system parameters, among other things, need to be made early on by system architects. SLX determines the impact of these various design decisions and parameter selections, while exploring different target architecture configurations and checks ... » read more

Inaccurate Assumptions Mean Software Issues

It doesn’t seem that long ago when features and functionality were being added to next generation processors and SoCs ahead of demand. Actually, I recall when new processors were released, embedded software developers were forced to think of innovative ways to exploit the new features in order to differentiate the product to not be left behind. Today, in many respects it seems as if the... » read more

Creating Software Separation For Mixed Criticality Systems

The continued evolution of powerful embedded processors is enabling more functionality to be consolidated into single heterogeneous multicore devices. Mixed criticality designs, those designs which contain both safety-critical and non-safety critical processes, can successfully leverage these devices and meet the regulatory requirements for IEC safety standards and the highest level of ISO. Thi... » read more

Coherency: The New Normal In SoCs

We are not far from devices each handling 100 teraflops of compute, billions of pixels of display, hundreds of gigabits of connectivity, and terabytes of storage. Compared with current state-of-the-art mobile SoCs, these are increases of one or two orders of magnitude — at similar or preferably lower power consumption. SoC design is changing to meet this challenge. Multicore architecture i... » read more

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