Improved Efficiency

By Bhanu Kapoor
We constantly hear about process technology advances and their impact on power consumption of ICs, but the power management techniques have remained the same over last few process technology generations. Power gating, dynamic voltage and frequency scaling, and threshold voltage scaling have been the key power management techniques since the 90nm process technology. Clock gating and multi-Vt devices came earlier and continue to be used, as well.

Power management techniques aren’t about to change anytime soon, but a lot of work is being done in making these techniques more efficient at what do. Some of the inefficiencies come from the components that support power management techniques, such as the analog power supply chip commonly known as PMIC or Voltage Regulator Modules (VRMs).

These PMICs operate at much lower frequency than the typical processors they supply power to. The switching off and on of a power supply line is a much slower event compared to a clock period of a processor. This speed itself can become a bottleneck in the time granularity at which you can support power gating. Power gating is a technique that switches of power supply to different regions in the chip and eliminates leakage power consumption in those regions.

In a previous blog article about near-threshold computing, we discussed the importance of further scaling the voltage down to lower levels to make DVFS more effective. Even at higher voltages, it is well known that being able to scale voltage continuously, as opposed to scaling to a few discrete points, results in lower dynamic power. In the scenario of typical SoCs today, this amounts to supplying different cores and regions using independent supplies that can operate at multiple voltage operating points.

In order to remedy the issues discussed above, you want a PMIC to be integrated on the processor, but that’s quite challenging to carry out cost effectively on the leading-edge process technology nodes. Voltage regulators are typically off-chip due to the large inductive and capacitive elements they tend to use, and on-chip implementation becomes costly at the leading edge.

An alternative is to use on-package CMOS voltage regulators. Intel’s Haswell processor (the Intel ‘tock’ for its Tri-gate22nm process technology node, where the Ivy Bridge was the ‘tick’) utilizes such an integrated VRM. This also will eliminate the space used by VRMs on the board as VRM is integrated on the processor package. This is a programmable chip with 20 power cells, each capable of supporting 16 phases of supply and up to 25A current. This provides plenty of options to supply each of the cores and other power domains independently, in addition to being able to switch the supply off much more quickly to power gate more often.

—Bhanu Kapoor is the president of Mimasic, a low-power consultancy.