System Level Power Integrity Verification For Multi-Core Microprocessors With FIVR

A technical paper titled "A Compressed Multivariate Macromodeling Framework for Fast Transient Verification of System-Level Power Delivery Networks" was published by researchers at Politecnico di Torino and Intel Corporation. Abstract: This paper discusses a reduced-order modeling and simulation approach for fast transient power integrity verification at full system level. The reference str... » read more

Improved Efficiency

By Bhanu Kapoor We constantly hear about process technology advances and their impact on power consumption of ICs, but the power management techniques have remained the same over last few process technology generations. Power gating, dynamic voltage and frequency scaling, and threshold voltage scaling have been the key power management techniques since the 90nm process technology. Clock gating... » read more