Improving Reliability

By Dina Medhat
Advanced IC designs implement complex strategies to minimize static and dynamic power. Mixed-signal designs typically require different supply voltages for the analog and digital portions of the design, and even all-digital ICs can have many power domains and operating voltages. Typically, some signal lines cross from one domain to another and special interfaces and “voltage protection schemes” must be provided. Applying a reverse bias to a transistor substrate increases the threshold voltage and reduces current leakage, but also creates the opportunity for new connectivity errors that can result in severe leakage.

The close proximity of so many supply voltages creates the potential for both catastrophic and degradation failures if designs are not comprehensively verified. Because of the delayed impact of some of these design errors, it becomes a reliability issues for sensitive applications in the automotive, medical, and communications markets. Consequently, there is a growing demand from the semiconductor industry for robust verification tools that understand power intent and can identify a variety of power-related problems at the system-on-chip (SoC) level, such as incorrect supply routing, static leakage issues, missing level shifters, and others.

Almost every engineer who designs and verifies low power and mixed signal designs today needs to check the following:

1. Over-voltage on thin-oxide MOS devices: All thin-oxide transistors in the IC must be checked to verify that the voltages across all device terminals are within the device’s maximum specification; violations are usually the result of incorrect domain crossings or supply bus connections, and can result in immediate catastrophic failure, or long-term degradation leading to failures in the field.
2. Missing or incorrect level shifters: Detect missing or incorrectly implemented low-to-high or high-to-low level shifters on the boundary between different voltage domains.
3. Missing or incorrect isolation cells: Detect missing or incorrectly implemented isolation cells on the boundaries between switch-off and power-on domains.
4. Issues related to body biasing: Compare voltages between source and bulk terminals and raise an error under specific conditions.
5. Electrically floating MOS gates: Detect MOS devices with gates that don’t see any defined voltage, which can result unpredictable current leakage.

Until recently, the options available for automatic power-aware verification were limited because the requirements are substantially different than what traditional layout design rule (DRC) checkers and layout versus schematic (LVS) checkers provide. Consequently, these checks were done manually with the aid of simple scripts. However, with the growing scale and complexity of ICs, this approach is no longer desirable. Designers need robust automation to address the power checking challenges.

Power-aware checking requires a tool that can use the design’s net list to recognize specific circuit topologies, such as level shifters, I/O drivers, and other structures, and then relate those to the corresponding GDS geometries making up the layout to make sure those specific elements have been included and have been implemented correctly. Unlike the foundry DRC decks, the definition of these checks do not all come from the foundry, but must be tailored to the specific design styles and practices of the designer’s company, so the tool must be highly flexible and easily programmable.

To perform power-aware checks, designers also need to know the voltage at every internal node in the design (Figure 1). Achieving this with exhaustive dynamic simulation is simply not practical at the full chip level due to the turnaround time involved. If the design is a large SoC, it may not even be possible to simulate it in its entirety. Therefore, we need a way to determine the voltages at all internal nodes statically. A power-aware checking tool must also be able to statically propagate voltage values from the various supplies to every node in the circuit in order to enable a variety of electrical overstress (EOS) checks.

Figure 1: Calibre PERC can assign voltages to all internal nodes of an SOC using an efficient static analysis method, enabling efficient electrical overstress reliability checks.

Power-aware verification is a challenging task in large SoCs at advanced technology nodes, and I’ve just touched on some of the new tool requirements here. For additional details on checking challenges and how to use a power-aware checking tool such as Calibre PERC, see the article “Power-Aware Verification in Low-Power ICs” in Chip Design magazine (http://chipdesignmag.com/display.php?articleId=5163).

—Dina Medhat is a senior technical marketing engineer for Calibre Design Solutions at Mentor Graphics.