It’s Never Too Early

Doing more low power static checking earlier in the implementation flow can save big on the back end.

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My previous postings discussed the importance of native low-power capabilities and coverage in simulation flows. The complement to this is incorporating complete and thorough low power checking throughout the design and implementation flow, and find and fix as many low-power bugs as possible before simulation. With the right checking tools and proper deployment, doing so enables the possibility of real time savings in the hardware verification flow, allowing more time for validation tasks (emulation, prototyping, software development) and even bringing in schedules.

Bring in schedules with pervasive low power checking early in design flows

Bring in schedules with pervasive low power checking early in design flows

This is much easier said than done. Effective low power static checking has been available for several years, but broad deployment and use has been limited. In talking to many customers over the past 18 months, the main technical reasons were:

  • Barriers to adoption from lack of integration and compatibility with implementation flows;
  • Too much overhead in design cycles from long runtimes, especially as complexity and design sizes are exploding;
  • Impact on engineering productivity from tedious sifting through excessive “noise” in violation reporting, and
  • Difficulty in finding root causes of bugs from out-of-context debug.

We’ve been working closely with customers in the past 18 months to meet these challenges with a next-generation product named Verdi Signoff-LP. The Verdi Signoff technology platform was developed by Synopsys specifically to enable the creation of static verification products capable of handling the design size and complexities of the most advanced SoCs, while delivering the features and performance needed to allow wide adoption and use in both design and verification teams. Related to the key challenges above, Verdi Signoff-LP has proved to be able address the toughest customer concerns.

Ease of use and adoption: In contrast to current low power static checking products, the Verdi Signoff-LP use model is built to be directly compatible with Design Compiler and IC Compiler. Verdi Signoff-LP commands, scripts and flows will be instantly familiar to users of DC/ICC. Correlation to implementation results is far improved also with use of common front ends and hardware inferencing. Tightly integrating the low power static checking activity into the implementation flow was crucial, and Verdi Signoff-LP supports the following simplified and efficient flow:

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Minimizing impact on design cycles: We are seeing customer designs with up to hundreds of millions of instances, and supporting early low power verification requires the ability to quickly and economically process SoCs and sub blocks of this magnitude. Fast runtime is critical to enable engineers to maintain efficient design cycle times, and high capacity is important to allow design teams to use mainstream compute hardware. The Verdi Signoff technology platform provides state-of-the-art database and static engine technologies, and Verdi Signoff-LP is showing performance and capacity capable of checking today’s huge designs, and scale for next-generation designs to come.

Reducing tedious and inefficient tasks: As I mentioned above, one of the most consistent requests from talking to customers is reducing the quantity of violations in reports generated by low power static verification. It is very common for one bug to cause a cascade of subsequent violations, and today’s existing tools do very little to filter what can be enormous (hundreds of thousands or even millions of individual violations) reports. Verdi Signoff-LP was constructed to both to track the root cause bugs and provide unique reporting features that enable “compression” of violation reports. We have seen customer results that show up to 10X reduction in the volume of violations, and give users much faster ability to find root cause issues. The example below shows how a simple missing ISO strategy in the UPF may cause a cascade of 128 subsequent low power static checking violations. However, with Verdi Signoff-LP’s violation compression features, the root cause violation is found and reported, and the subsequent violations may be hidden or demoted—automating a previously tedious designer activity.

This is just a brief introduction to Synopsys’ efforts to help customers do much more verification early in design cycles in order to reduce verification effort and time overall. Low power static checking is an important part of today’s flows, and doing much more much earlier in the implementation flow can eliminate low power bugs that would otherwise need to be found and fixed in simulation. However, we’ve seen challenges inhibiting wide adoption, and these were key drivers for the development of the Verdi Signoff platform and Verdi Signoff-LP. We will certainly be talking more about Verdi Signoff-LP going forward, including much more about the new and advanced low power checking capabilities it provides.

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