中文 English

Joint Optimization Of Hardware And Compiler

Modeling AI accelerators using Platform Architect.

popularity

ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, operating systems and networking.

This presentation proposes a novel approach for joint optimization of algorithms/compilers and hardware architecture. The top-down/integrated approach that leverages the latest machine learning framework/compilers, combined with the underlying hardware architecture design could be one of the most promising directions to boost the productivity/quality-of-result for AI chip designs.

To read more, click here.



Leave a Reply


(Note: This name will be displayed publicly)