Jumpstarting The Automotive Chiplet Ecosystem

The automotive industry stands on the cusp of a technological renaissance, ushering in an era where vehicles aren’t just tools of transportation, but interconnected nodes within a vast network of software-defined mobility. Central to this transformation is the concept of chiplets—miniaturized, modular components that can be mixed, matched, and scaled to create powerful, application-specific integrated circuits (ASICs).

In a major push to advance the automotive chiplet ecosystem, Cadence Design Systems and Arm have teamed up to slash development time, accelerate product innovation, and foster a new era of collaboration. Here’s a detailed look at how the resulting chiplet reference design and software development platform are paving the way for the next phase of automotive innovation.

The need for speed in auto-component innovation

When it comes to speeding up innovation, safeguarding lives on the road and enabling the vision of autonomous driving, the automotive industry has zero margin for error. Yet, the industry is increasingly vulnerable to the notoriously long and arduous design cycles of automotive semiconductor components—a stark contrast to the breakneck speed at which the consumer technology sector operates.

Chiplets present an attractive solution, promising to cut down development cycles by enabling concurrent design and assembly of multiple chips using a common, standardized interface. This methodology of system-on-chip (SoC) development can reduce time to market significantly. However, the challenge lies in ensuring that chiplets from different vendors and with different applications can seamlessly interoperate.

Enter the Cadence and Arm collaboration, which not only addresses these interoperability challenges but also provides a much-needed head start to the otherwise complex and time-consuming path of automotive chip development.

The cornerstones of the chiplet reference design

At the heart of the Cadence and Arm collaboration is a chiplet reference design built specifically for advanced driver assistance systems (ADAS). Boasting a scalable chip architecture and interface interoperability, this reference design is not merely a blueprint but a milestone in automotive chip development methodology.

The solution architecture aligns with the Scalable Open Architecture for Embedded Edge (SOAFEE) initiative, introducing a new standard for software-defined vehicles’ chip and interface designs. By doing so, it lays a sturdy foundation for industry-wide collaboration, fostering an environment where innovation and integration go hand in hand.

The reference design’s role

The chiplet reference design is not merely a starting point for chip development. It’s the benchmark against which future innovations in the sector will be measured. It also provides a common frame of reference for interoperability testing—a crucial step in enabling chiplets from different vendors to work seamlessly together.

Cadence’s part in the reference design is pivotal. The company provides a spectrum of tools, IP portfolios, and services that encompass the entire chip design and development process. Additionally, Cadence contributes IP for the silicon-proven Universal Chiplet Interconnect Express (UCIe) for high-performance die-to-die applications, underpinning the scalability and performance of the chiplets.

The advanced driver assistance reference design thus is not only a design to be evaluated on its own merits but is also an environment in which members of the ecosystem can evaluate their own innovations. Cadence expects customers to use and extend individual chiplets and also use the reference design to verify ecosystem interoperability. To support this innovation and interoperability the designs will be available for testing in Cadence verification tools.

The IP foundation

With a toolkit ranging from virtual and hybrid platform creation to an extensive I/O IP portfolio, and a suite of compute IP solutions, Cadence is not just providing the hardware tools; it’s creating an entire ecosystem that future automotive chiplets can plug into seamlessly.

In addition, Cadence offers end-to-end silicon design services for SoC customer enablement, to bring deep IP knowledge and design best practices to the table.

Silicon-proven UCIe high-performance interconnect IP

After designing three generations of our proprietary UltraLink die-to-die interconnect solution, which is now in high-volume production with multiple customers, we’ve gained a lot of experience in die-to-die chip design.

At the recent Chiplet Summit 2024 in San Jose, Cadence demonstrated the first test chip that includes seven chiplets, each with two UCIe PHY blocks. We showcased an industry-first eye-diagram measurement of a die-to-die interconnect with speeds of up to 16GT/s on an oscilloscope.

By successfully bringing up and transmitting data across the entire range of interconnect distances, including short, medium, and long-reach channels Cadence demonstrated its ability to design a high-performance IP that meets and exceeds specifications.

This successful implementation of UCIe IP on first-pass silicon in TSMC N7 is a milestone in die-to-die connectivity!

A digital twin that defies conventional timelines

Perhaps the most revolutionary aspect of this reference design is the inclusion of a complementary software stack development platform—a digital twin that faithfully mirrors the behavior of the actual hardware design. This proxy software allows automotive engineers to start software development for new chiplets before the physical components are even available, thus significantly reducing design iterations and time to market.

This virtual platform stands ready to be deployed by early adopters, heralding a new age of test and validation that can be conducted in silicon, without the necessity of physical prototypes. With this, automotive designers are empowered to begin their software and hardware development concurrently and with unprecedented accuracy, leading to a significant reduction in costly and time-consuming re-design efforts.

Driving together into the future

In the increasingly intertwined world of automotive technology and semiconductor innovation, chiplets are not just a passing fad but the bedrock for the road ahead. The collaboration between Cadence and Arm is not merely about creating cutting-edge technology; it’s about reshaping an entire industry’s paradigm.

By providing a platform for harmonized development and a robust reference design that encourages diversity in the chip ecosystem, the two corporations aren’t just building towards a transitional phase in automotive electronic design. They are catalyzing the essence of what it means to drive—both as an experience and an industry.

Forging the chiplets of our transportation future

The ability to combine chiplets from different manufacturers into a single, cohesive unit offers OEMs and Tier 1 suppliers unprecedented flexibility and agility. It’s not just about slashing development time or achieving greater economies of scale; it’s about setting the stage for a more modular, interoperable, and markedly intelligent tomorrow.

The strides made by Cadence and Arm in jumpstarting the automotive chiplet ecosystem transcend the mere act of collaboration—they epitomize a shared vision of a safer and smarter connected automotive world.

With the convergence of Cadence’s chiplet flow and IP, and Arm’s Automotive Enhanced IP solutions, automotive chiplets will play a key role in enabling the software-defined vehicle. And as the industry adapts to this revolutionary shift, the implications for cost, efficiency, and innovation could truly transform the automotive industry.