Making DFM Work Better

By Ann Steffora Mutschler

At 65nm, design for manufacturing optimization and analysis has mostly been an afterthought. At 40nm and beyond, DFM has been pushed well up into the design phase.

There are good reasons for this shift. What emerged at the 65nm node were signoff tools that understand manufacturing used in semiconductor design, said Manoj Chako, a product director for digital sign-off solutions at Cadence Design Systems. DFM used to occur post-DRC and included the work done by the foundries. At 40nm, ‘design-side DFM’ is forcing design teams to take into account the lithography, CMP (chemical mechanical planarization) and electrical (parametric yield) issues.

“The systematic effects on the layout have now become a prominent problem,” Chako said. Among the problems to surface at 40nm and beyond are parametric yield due to tight geometries and the very tight pitch in designs, performance issues caused by strict design rules and the addition of stress in designs that is being added to improve the mobility and performance of transistors.

From a high level, this is being caused by a fundamental disconnect. The process geometries are scaling but the wires do not scale uniformly. The wires are getting narrower, which is causing a problem with cross-talk, but they’re not getting as short as everyone expected, said Rob Knoth, technical product manager for Magma Design Automation’s design implementation tools.

Moving from 65 to 40 and 28nm has driven other changes, including the penalty of a via. “There are now rules governing redundant vias and the shape of a via, for instance, said Knoth. “Some foundries change their recommendation for what a good via would look like. This can be multiple square or rectangular cuts.”

Knoth said he is also concerned about stress-induced lithography violations at 28nm, a lot of OPC (optical proximity correction) checks, and very complicated end-of-line rules. “At 65-nm, things were a little more vanilla. People were looking at dummy metal to improve the gradient across the chip. They were definitely looking at redundant vias but it wasn’t nearly as critical as it is at 40nm and 28nm, both from a manufacturing standpoint and a timing standpoint.”

These technological impacts have changed the way semiconductor implementation is performed, noted Sudhakar Jilla, director of marketing for Mentor Graphics’ place and route products. At 28nm it’s important to have the router be able to call the signoff quality engine during the routing phase. Typically what happens is that once routing is finished, DRC (design rule checking) and LVS (layout vs. schematic) are run. At 65nm, the DFM analysis was an afterthought once the design was judged DRC and LVS clean. At 40nm and beyond, it needs to be considered much earlier in the flow or it will cause some very late stage surprises that will make recovery difficult, he said.

Jilla said that for one 28nm library a customer ran the design through the flow and performed the LFD (litho friendly design) analysis. It showed a number of L1 hot spot errors due to fidelity issues of the manufacturing process.

“This occurred one week before the tapeout, and if they had to go and fix all of the violations it would have taken a few more weeks and would have to be done by hand,” he said. “We are working on a technology for the router – which is utilized four to six weeks before tapeout – that can invoke the same LFD engine inside the router. Once the router is done routing it asks if it is LFD clean. If yes, it is done. If not, the fixes are made at that time. If you don’t have a solution where the router can take advantage of the signoff engines, you are going to have to wait until the last minute or let the design go as it is, taking a risk on the yield.”

Knoth said that one of the big things Magma is doing, especially moving from 40nm to 28nm, is changing some of the cost functions that are driving the tool, and looking at things like spreading wires earlier so that congested hot spots are not created. The company also is building intelligence earlier in the cycle to avoid future manufacturing problems.

“It’s hammering more on that ‘correct-by-construction’ concept,” Knoth said. “The cost of fixing a problem once you analyze it is huge. That being said, though, the other main effort that we are working on for 28nm is building a better infrastructure so that timing can be considered as you are going in and fixing lithography problems.”

In Magma’s place and route toolset everything is integrated: the timer, the DRC checker, the router, etc., so the router can call the other engines as it is making decisions. If it is reordering wires, or is jogging something to make it more litho-friendly solution, it understands the timing impact of that because you can’t just fix DFM.

“That’s a very big fallacy that I think happened early on when a bunch of DFM solutions hit the market at 65nm,” Knoth said. “Everyone was just looking at DRCs and DFM and we made sure that timing was also part of that, so that as we went off to hammer on those problems we weren’t creating a new timing violation that would cause you to rip up and rebuffer a whole net.”

The foundry effect
“DFM in general is a concept that is never going to go out of style,” Knoth continued. “The frustrating thing about DFM is that it just reflects a foundry’s lack of familiarity with a process. As a process matures the foundry figures out what yields better and what doesn’t. They make hard rules to improve the yield and a lot of the soft rules that are needed for DFM, those go away.”

At 65nm, TSMC and most of the foundries had DFM as a recommended rule, but it was not a mandatory signoff check. But starting at 40nm, most of the foundries are making DFM handoff mandatory.

“What that tells you is that the foundries are now starting to realize you can’t just squeeze the DRC rules some more and hope it addresses DFM success,” Jilla said. “DFM is a big enough issue that they can’t hide it in the back. And what that indirectly means is that although the customers say they do run a DFM check and find 20 or 30 LFD hot spots. or you do the critical area analysis and there are a lot of opens and shorts, what do you do about it? That’s where the router comes into play and the designer needs to have a router that can respond to these sign-off checks and give a clean design that not only is DRC/LVS and timing clean, but also DFM clean.”