Making IP Tradeoffs For Power

By Ann Steffora Mutschler
Power may be expensive, but just turning off sections of a chip, lowering the voltage or using low-power manufacturing processes have their own costs.

Whether using power, or managing it, there is a price. As Brani Buric, executive vice president at Virage Logic says, “Power is not free.” But fortunately, other things in a design can be traded off in order to achieve the desired power budget.

Specifically, power can be traded off for the design domain, area and performance. Moreover, given the state of advanced technologies, designers also can choose between different process nodes that will give, for the same area, different power/performance tradeoffs.

Buric noted those tradeoffs can be achieved on different levels of design abstraction with an equal opportunities on every level. “For example, when a company like Virage Logic or ARM is designing a microprocessor that is delivered in RTL form we can still trade off performance for power or, in certain cases, area for power. Then, if you go down in abstraction, when it comes to physical IP, you have even more nodes where you can trade off performance for power, area for power, etc.”

A lot of power-saving techniques can be implemented in a memory, for example, but if RTL designers are not aware of power saving techniques they will implement a memory that doesn’t use those techniques.

“Designers or systems architects have to decide on that level where they are going to do tradeoffs between power, performance and area,” he said. “Based on that, they can select optimal IP that fits in their power algorithm concept. From our side, we essentially have all of our physical IP designed that way so that designers have ‘knobs’ and a dashboard of options to tune power – both dynamic and static (leakage) – to the desired level, trading off mostly performance and in certain cases, area.”

Competing IP provider Synopsys Inc. gets requests from customers for the lowest power with aggressive targets for area and other performance metrics, according to Navraj Nandra, director of product marketing for analog/mixed-signal IP. These requests require the IP vendor to simultaneously optimize for power and these other requirements. Specifically for analog/mixed-signal IP, this is achieved through design techniques such as low-power transmitters for USB and high speed SERDES, lower amplitudes for the I/Os in DDR and simplified analog stages with reduced biasing in data converters.

Nandra noted that these techniques deliver the lowest power but do not necessarily trade off performance, and that the biggest trade-off is speed and transmission distance when low power techniques are adopted in IP development.

Software analysis tools help make power tradeoff decisions
While Tensilica looks at power from the architectural level—if certain design decisions are made as to configuring a processor to fit a particular algorithm, then benefits of low-power can be had by being able to run the processor at a much lower clock rate than it would otherwise — the company has profiling tools to allow engineers to figure out what those instructions are that would help benefit optimizing the processor to fit the algorithm, according to Chris Jones, director of product marketing at Tensilica.

At the physical design layer, Tensilica has an energy estimator tool called Xenergy that gives real-time feedback on the relative power numbers based on the configuration attributes for chosen processors. Specifically, Xenergy gives dynamic energy consumed on a cycle-by-cycle basis, Jones explained.

“[SoC engineers] can take this algorithm, choose a processor with one set of attributes, render the energy estimator tool, and get a power number. If they want to add a couple of instructions or they want to grow the size of the caches or add a MAC instruction, they can then run the same algorithm again and run the Xenergy tool to see what power benefits they are able to gain by making those design decisions.”

Tradeoffs impact IP ecosystem
“We struggle with [making tradeoffs] today with our test chips because we don’t want to develop a complete SoC, but with our test chips we want to validate the technologies together and so fundamentally we are looking for functional things and best practices,” said Kevin Kitagawa, director of strategic marketing for MIPS Technologies. “Are we getting the fastest amount of performance? Absolutely not, because there are diminishing returns after you get to the 90% performance level. It is the same with power consumption: you can probably get 90% of the power savings out of a particular design, but the last 10% will take double the amount of effort. So we try to pick up where the knee in the curve is, where you’re starting to not get a lot out of the extra engineering effort.”

He noted that the availability of open source platforms such as Android is impacting the need to make tough design decisions.

“A lot of people are trying to squeeze in what used to be implemented in specific hardware. For example, people want to implement Android in a lighter sense, and in a cost structure that is probably one-third of what the requirements are for Android today. Instead of 256MB of main memory, they want to do it in 64MB of memory, so a lot of challenge is trying to get the benefits of Android into a cost structure that makes sense for them,” Kitagawa said.

It is possible to attain this, he said, but hard decisions would have to be made as to feature set and performance levels with some sacrifices along the way.

Whether it is sending in an expert or sending in software, there is opportunity on one side and a vital need on the other.