Making Too Much Noise

By Ed Sperling
For the better part of a decade talk about signal integrity in mixed-signal designs has been noticeably absent. That’s about to change.

Prior to the adoption of a 130nm process, many semiconductor companies actually went on record saying they were considering abandoning plans to ever put analog and digital on the same chip because the noise on digital would interrupt signals. The issue seemed to die down after that. But at 32nm it has shown up again, driven this time by a multitude of problems—some new, some old, and all of them made worse because there are fewer alternatives.

“The problem has always been there,” said Navraj Nandra, director of analog/mixed signal marketing at Synopsys. “But it has suddenly gotten worse because of the design interfaces at higher speeds. At 40nm and 28nm transistors switch faster. We also have 8 Gbps PCI Express [generation] 3 and DDR3. You have multiple lane configurations with PCI Express. Graphics cards use eight lanes. We’re connecting by 16s. But PCI can use 96 lanes.”

That’s a lot of noise on an advanced chip, where the wires are thinner and thinner at each node and components are packed together more tightly. If a single atom of deposition can change the functionality of a transistor, imagine what can happen when you start adding in parasitics and electromigration.

Power corrupts
If the only thing that changed in an SoC was the manufacturing process—doubling the number of transistors on a piece of silicon for every rev of Moore’s Law—then lowering the voltage would actually improve signal integrity. It isn’t that simple, however.

Adding in multiple voltage supplies increases the noise level on the chip. “At 28nm and beyond we’re seeing 800 millivolt supply voltages and threshold voltages of 300 millivolts,” said Aveek Sarkar, vice president of support at Apache Design Solutions. “Not only is the noise on the supply voltage increasing at each node, but the sensitivity is also magnified.”

The current is faster, the drive strength is higher, and voltage noise is higher. And the problem gets worse as you add in power gating and multiple power islands, all turning on and off unpredictably and intermittently in close proximity to each other.

It also gets worse when you bring the voltage regulators onto the chip from the PCB.
“That becomes a problem if you want multiple power domains on a chip,” said Qi Wang, technology marketing group director at Cadence. “The regulator is analog and noise becomes a problem. You’ve got big digital areas that generate noise. That can be a big issue, especially for the voltage regulator. People are now overdesigning chips and that’s creating more of a problem as more and more analog is put on the die.”

What’s in the package?
At least part of what will have to change in many designs is the package, which frequently is an afterthought for the total design and most often based on price rather than its effect on the operation of an SoC.

“People want to put in a cost-effective package to cut their costs, but that kind of package was not designed to handle high-speed I/O,” said Synopsys’ Nandra.

That can create a huge problem for signal integrity. But packaging is typically the victim of a silo effect. It’s not part of the up-front architectural decision and it’s not part of the SoC model being created.

“The focus is on the semi design, but the package design is just as important,” said Apache’s Sarkar. “There are no so many different packages that it’s confusing. You have to worry about whether it’s four layers or two layers, and if you have 80 different power domains the package can get very complex. We’re seeing wireless chip packages now that are not uniform.”

Living in a material world
The substrate material is equally important in signal integrity. CMOS has been getting mixed reviews, in part because it’s a proven low-cost material with excellent conductivity. But it’s not especially good for mixed-signal applications at advanced nodes. So while Intel may get away with using it for a predominantly digital processor, an SoC has completely different needs—and different economics.

Materials such as silicon on insulator and gallium nitride do improve signal integrity, but that improvement comes at a price. SoI is the less expensive of the alternatives, and has been proven to work in designs since 65nm by IBM, AMD, and some of the partners in the Common Platform ecosystem.

The problem is that architects and designers don’t necessarily know what kind of substrate or package they will need up front because the IP they buy from third parties doesn’t include information about noise.

“IP vendors need to provide enough data constraints in their libraries to say how the IP can be used properly,” said Cadence’s Wang. “You need to know, for example, ‘For this ping it can be this close to a digital component,’ or ‘Do you put this within this distance of I/O.’

He noted this is an important new wrinkle in IP integration. “’We need a holistic solution for the ecosystem of IP providers. We need a better model, and we need EDA tools that are better and faster at noise analysis.”

3D stacking
What has many experts particularly worried is the effect of 3D stacking on signal integrity. While most of the focus has been on thermal effects—hot spots caused by putting two or more chips together—there is a magnified effect for noise.

Vendors such as Qualcomm, Freescale and IBM expect 3D stacking to begin rolling out in late 2011 or early 2012—roughly one year from now. From there the approach is expected to grow rapidly, in large part because it shortens the distances that signals need to travel, which in turn boosts performance while lowering the power needed to drive those signals.

But moving the mass SoC market in this direction compounds many of the issues for signal integrity that exist with packaging, substrates and proximity—while adding new ones.

“With a through-silicon via, the power noise is much worse,” said Apache’s Sarkar. “TSVs brings signals closer together, but the silicon substrate is not stacked in terms of coupling with the TSV. So how do you model this?”

Synopsys’ Nandra noted that 3D shifts the problem from the packaging inside the SoC. “With a stack die you’re communicating inside the die, so the I/O problem is less,” he said. “But within the die now you have interactions between platforms. Basically you’ve just shifted the problem.”

Conclusions
None of this has been lost on the tools vendors. Many are scrambling to bring new tools to market that can analyze noise, heat, IP integration problems, as well as the ability to model all of it.

But these are complex issues. There is no single tool that can do everything, and so far these are well outside of existing design flows. Moreover, there are no standards that effectively address the dynamics of using IP in a high-density, highly noisy environment that includes voltage changes, rapid power-up and power-down modes, SerDes and high-speed I/O, and the effects of packaging and substrates.

These are challenging problems that have to be deal with up front and together, both by design teams and by ecosystems that include IP vendors and foundries. And so far, semiconductor makers have merely scratched the surface.