Managing The Path Of Least Resistance

The concept is simple enough, but reality looks a lot different for advanced SoCs.


One of the great lessons of physics is that the natural order of things is the path of least resistance. Liquid flows to the lowest spot unless restrained by some sort of dam. Electrons flow through the channel with the least resistance and the highest conductivity.

There are a couple of twists in the low-power engineering space, however, that can be classified as supra-natural. One is that electrons only move at a specific rate, and only sometimes. The complex series of voltage islands running different voltages in a single SoC, clock gating, power islands, and now dynamic voltage frequency scaling, is a way of damming up path of least resistance. But in the case of electrons, that’s not so easy at advanced process nodes where the distances between wires have shrunk to widths that can only be seen with advanced microscopy.

The promise of 3D structures such as FinFETs, the insulating properties of fully depleted SoI, and exotic technologies such as air-gap insulation is to provide additional tools to continue damming up the electrons and slowing the leakage as process nodes continue to shrink. The question now is when do the walls become so thin that leakage is impossible to stop.

The second twist is that electrons can be channeled according to where they’re needed most. This sounds simple enough in theory, but the hard part is understanding exactly how much performance and energy is needed for a specific task. One size may fit all, but if the goal is to minimize the flow of electrons that’s not exactly the most efficient approach.

To some extent, this is a supply chain issue as much as a business issue. While a processor may run a single application faster, a dual-core processor may run it slower than a single-core processor if the frequency is lower. But with either accelerators or more efficient software code—or hardware built for specific software in mind—performance may go up significantly with far less energy consumed.

These are complex issues, and they become more complex as we continue to cram more onto every SoC. While we may see billion-gate processors in the near future, we also are seeing SoCs with 100 million gates. And both of them can easily increase by an order of magnitude over the next couple of years. Managing the flow of electrons so they don’t take the path of least resistance all the time will become increasingly challenging. And for all the simplicity in this concept, it seems to be
getting very complicated.


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